SiC MOSFET Fuse Element for Gate-Source Short Isolation
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Solution Overview
Problem
Silicon carbide (SiC) MOSFET devices face defects due to debris deposition during manufacturing, leading to short-circuit issues between the gate and source regions, causing device failure and increased manufacturing costs, as commercially available MOSFET devices are rejected if any transistor fails.
Innovation Solution
Incorporating a fuse element between the gate and generator to interrupt the electrical connection in case of short-circuit current, designed to melt or change state and isolate the defect, with a buried cavity to contain the melted material and prevent structural damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If debris is released during SiC wafer manufacturing, then manufacturing process continues, but short-circuit defects form between gate and source regions
Solution Approach 1:
The patent applies preliminary action by forming a protective oxide layer on the SiC wafer surface before the debris contamination problem occurs. This oxide layer is created through thermal oxidation or chemical vapor deposition, establishing a barrier that prevents debris from directly causing short-circuits between the gate and source regions during subsequent manufacturing steps.
Solution Approach 2:
The patent uses an intermediary approach by introducing a specially designed gate oxide layer with controlled thickness and properties between the gate region and the SiC substrate. This intermediary layer acts as a buffer that can accommodate debris without allowing direct electrical contact, thus preventing short-circuits while maintaining device functionality.
2Reliability
If a transistor fails due to short-circuit, then device rejection occurs, but manufacturing costs increase
Solution Approach 1:
The patent applies segmentation by dividing the gate structure into multiple independent regions with individual oxide layers. This allows localized defects to be contained within specific segments rather than affecting the entire device, enabling selective repair or rejection of only the defective portions while salvaging functional transistors.
Solution Approach 2:
The patent implements beforehand cushioning by creating a robust gate oxide layer with sufficient thickness and quality before any potential debris contamination or manufacturing defects occur. This cushioning layer provides a margin of safety that absorbs the impact of potential defects, preventing catastrophic failures and reducing device rejection rates.
3Object-affected harmful factors
If gate oxide layer is formed to prevent defects, then insulation is improved, but leakage paths may still form through imperfections
Solution Approach 1:
The patent applies composite materials by combining multiple layers with different properties - a thick initial oxide layer for bulk insulation, followed by a thinner refined oxide layer for surface quality, and potentially additional protective layers. This composite structure leverages the advantages of each layer to achieve both high insulation and low leakage characteristics.
Solution Approach 2:
The patent uses parameter changes by carefully controlling the thickness, composition, and formation conditions of the gate oxide layer. By optimizing these parameters through thermal oxidation or chemical vapor deposition processes, the oxide layer achieves the right balance between providing sufficient insulation thickness and maintaining uniform quality to prevent leakage paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fuse effectively isolates the short-circuit, preventing device failure and allowing for the restoration of functionality by disconnecting faulty transistors, maintaining insulation characteristics and minimizing current loss, while the buried cavity manages the melted material without structural compromise.
Implementation Method 1
The protection element (21) is configured to go from the solid state to a melted or gaseous state, interrupting said electrical connection
Implementation Method 2
in response to a leakage current (iSC) through said protection element (21) greater than a critical threshold
Implementation Method 3
a buried cavity (69) in the solid body (48) accommodating, at least in part, said protection element (21)
Data Source
AI summary
SiC-based MOSFET electronic device comprising: a solid body; a gate terminal, extending into the solid body; a conductive path, extending at a first side of the solid body, configured to be electrically couplable to a generator of a biasing voltage; a protection element of a solid-state material, coupled to the gate terminal and to the conductive path, the protection element forming an electronic connection between the gate terminal and the conductive path, and being configured to go from the solid state to a melted or gaseous state, interrupting the electrical connection, in response to a leakage current through the protection element greater than a critical threshold; a buried cavity in the solid body accommodating, at least in part, the protection element.