SiC MOSFET Gate Dielectric Stack for Threshold Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current silicon carbide (SiC) MOSFET devices face challenges with high on-state resistance and threshold voltage instability due to the limitations of silicon oxide gate dielectrics, which require high-temperature annealing and result in disordered interfaces and high electric field stress, leading to poor reliability and leakage current issues.
Innovation Solution
A multilayer gate dielectric stack comprising silicon oxide, hafnium oxide, and aluminum oxide layers is used, with specific thickness and bandgap values to create a high-density electron trap layer, reducing thermal budget and enhancing dielectric reliability, while maintaining low on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon oxide (SiO2) is used as gate dielectric in SiC MOSFETs, then the device can be manufactured by thermal oxidation of SiC, but the interface state density is 2-3 orders of magnitude higher than SiO2/Si stack, resulting in poor channel mobility and threshold voltage stability
Solution Approach 1:
The patent uses a composite gate dielectric structure consisting of a SiO2 layer combined with a silicon oxynitride layer. This composite structure leverages the ease of manufacturing SiO2 through thermal oxidation while the silicon oxynitride component reduces interface state density, thereby improving threshold voltage stability and channel mobility without sacrificing manufacturing simplicity.
Solution Approach 2:
The patent modifies the gate dielectric composition by introducing nitrogen into the oxide matrix to create silicon oxynitride. This parameter change (adding nitrogen) reduces the interface state density at the SiC interface while maintaining the beneficial thermal oxidation manufacturing process, thus resolving the contradiction between ease of manufacture and device reliability.
2Manufacturing precision
If high-temperature annealing (>1100°C) is performed to reduce interface state density, then channel mobility improves, but a disordered region with SiOx and C non-stoichiometric defects forms at the interface, negatively affecting stability
Solution Approach 1:
The patent changes the chemical composition of the gate dielectric by incorporating nitrogen to form silicon oxynitride. This compositional parameter change allows for reduced interface state density without requiring high-temperature annealing that would create disordered regions, thus improving interface quality while maintaining stoichiometric stability.
Solution Approach 2:
The silicon oxynitride layer acts as an intermediary between the SiO2 layer and the SiC substrate. It provides a transition zone that reduces interface state density without requiring the harmful high-temperature annealing process, thereby preventing the formation of disordered regions while still achieving good channel mobility.
3Ease of manufacture
If SiO2 gate dielectric is used, then manufacturing is simplified, but under high-voltage conditions the electric field in SiO2 is 2.5 times higher than in SiC, subjecting the dielectric to high-stress and poor-reliability conditions
Solution Approach 1:
The patent employs a composite gate dielectric structure where the silicon oxynitride layer has different electrical properties than pure SiO2. This composite structure distributes and reduces the electric field stress compared to pure SiO2, lowering the maximum electric field from 2.5 times SiC's field to a more manageable level, thereby improving dielectric reliability under high-voltage conditions while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the threshold voltage and reduces on-state resistance, improving the reliability and stability of SiC MOSFET devices by combining high permittivity and bandgap properties, limiting ringing phenomena and enhancing channel mobility.
Implementation Method 1
a first insulating layer (102) in contact with the semiconductor body (48; 68), having a first bandgap value and a first thickness, configured to be traversed, by tunnel effect, during use, by electric charge carriers coming from the semiconductor body (48; 68)
Implementation Method 2
a second insulating layer (104) on the first insulating layer (102), having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness, configured to form a potential well for said electric charge carriers
Data Source
AI summary
Electronic device comprising: a semiconductor body, in particular of Silicon Carbide, SiC, having a first and a second face, opposite to each other along a first direction; and an electrical terminal at the first face, insulated from the semiconductor body by an electrical insulation region. The electrical insulation region is a multilayer comprising: a first insulating layer, of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer on the first insulating layer, of a Hafnium Oxide; and a third insulating layer on the second insulating layer, of an Aluminum Oxide.