SiC MOSFET Gate Heterostructure for Low On-Resistance
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Solution Overview
Problem
Current silicon carbide (SiC) MOSFETs face reliability issues, high specific on-resistance, and high costs due to low inversion-layer carrier mobility, making them unsuitable for high-power applications like motor drive control, while SiC JFETs have challenges with normally off operation and low threshold voltages.
Innovation Solution
The development of a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) with a gate structure comprising a gate oxide layer, an aluminum nitride layer, and a p-type gallium nitride layer, which includes a lateral built-in channel with a p-type AlGaN gate and an AlN buffer layer, providing high threshold voltage and low interface trap density, enabling efficient operation with low on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If SiC MOSFET designs are used, then the device can be normally off under zero-bias, but reliability issues occur due to overstress of gate oxide and low inversion-layer carrier mobility resulting in high specific on-resistance
Solution Approach 1:
The patent employs a composite gate structure consisting of multiple layers including gate oxide, aluminum nitride, and gallium nitride. This composite material approach allows the gate structure to simultaneously provide the necessary electrical insulation and mechanical stress management, resolving the reliability issues of conventional single-material gate oxide structures while maintaining normally off operation capability.
2Reliability
If device size is increased to achieve lower channel resistance, then specific on-resistance decreases, but device area and cost increase
Solution Approach 1:
The patent utilizes parameter changes in the gate structure, specifically employing aluminum nitride and gallium nitride layers with optimized thicknesses and material properties. These parameter adjustments enable enhanced carrier mobility and reduced channel resistance without requiring proportional increases in device area, thus achieving lower specific on-resistance with compact device dimensions.
3Reliability
If SiC JFETs are used, then bulk carrier mobility is much higher resulting in lower specific on-resistance, but normally off operation is problematic and threshold voltages are low
Solution Approach 1:
The patent segments the gate structure into distinct functional layers: gate oxide for insulation, aluminum nitride for stress management and mobility enhancement, and gallium nitride for threshold voltage control. This segmentation allows each layer to independently optimize its function, achieving high carrier mobility and proper threshold voltage characteristics while enabling reliable normally off operation that pure JFET structures cannot provide.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SiC MOSFET achieves near-theoretical performance in blocking voltage and on-state resistance, allowing for high operation currents with a small device area, reducing costs and improving reliability for high-power applications.
Implementation Method 1
a gate structure that includes a gate oxide layer, an aluminum nitride layer disposed on the gate oxide layer, and a gallium nitride layer of the second conductivity disposed on the aluminum nitride layer
Data Source
AI summary
In a general aspect, a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) can include a substrate of a first conductivity type, a drift region of the first conductivity type disposed on the substrate, a spreading layer of the first conductivity type disposed in the drift region, a body region of a second conductivity type disposed in the spreading layer, and a source region of the first conductivity type disposed in the body region. The SiC MOSFET can also include a gate structure that includes a gate oxide layer, an aluminum nitride layer disposed on the gate oxide layer, and a gallium nitride layer of the second conductivity disposed on the aluminum nitride layer.