SiC MOSFET Gate Insulation via Polysilicon Oxide Etching
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Solution Overview
Problem
The challenge in manufacturing semiconductor devices using silicon carbide (SiC) substrates is the difficulty in forming thick field insulating films with high accuracy, which hinders miniaturization and performance enhancement due to the slow thermal oxidation rate of SiC, leading to low patterning accuracy and tapered structures during wet etching processes.
Innovation Solution
A method involving the sequential deposition of a thin silicon oxide film and a thicker polysilicon film on an SiC substrate, followed by dry etching to open the polysilicon film and wet etching to expose the silicon oxide film, allowing for the formation of a thick field insulating film and a thin gate insulating film with improved accuracy, enabling the embedding of the gate electrode under an eaves-like protruding sidewall of the insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal oxidation method is used to form field insulating film on SiC substrate, then insulating film can be formed, but the oxidation rate is extremely slow making it difficult to form sufficiently thick films
Solution Approach 1:
The patent changes the material parameter from SiC to Si for the field insulating film formation. By depositing silicon film in the field region and oxidizing it, the oxidation rate increases dramatically compared to SiC, enabling formation of sufficiently thick field insulating films within reasonable processing time while maintaining the required insulation performance.
Solution Approach 2:
The patent applies different material treatments to different regions: silicon film deposition and oxidation is applied specifically to the field region beside the gate insulating film, while the gate insulating film itself is formed separately. This local differentiation allows optimized processing for each region's specific requirements.
2Ease of manufacture
If wet etching is used to remove insulating film selectively, then gate insulating film can be formed, but patterning accuracy is low and tapered openings are formed
Solution Approach 1:
The patent changes the etching method parameter from wet etching to dry etching for removing the silicon oxide film. Dry etching provides anisotropic etching with vertical sidewalls, eliminating the tapered opening problem and significantly improving patterning accuracy compared to isotropic wet etching, while still enabling selective removal of the oxide film.
3Manufacturing precision
If thick field insulating film is formed by depositing insulating film and removing it selectively, then field insulating film with sufficient thickness can be formed, but device miniaturization is hindered due to low patterning accuracy
Solution Approach 1:
The patent changes the etching parameter from wet to dry etching, which provides the precision needed for device miniaturization. The dry etching process creates sharp, well-defined patterns that enable smaller device dimensions while maintaining the required thick field insulating film for proper isolation and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the miniaturization and performance of semiconductor devices by reducing the width of MOSFETs, improving integration, and maintaining high withstanding voltage, while preventing damage to the epitaxial layer and ensuring accurate processing of the gate electrode.
Implementation Method 1
forming a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film in sequence over an SiC substrate
Implementation Method 2
forming a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film in sequence over an SiC substrate
Implementation Method 3
opening the polysilicon film by a dry etching method
Implementation Method 4
successively opening the silicon oxide film by a wet etching method
Implementation Method 5
it is difficult to form a field insulating film having a LOCOS (Local Oxidation of Silicon) structure
Data Source
AI summary
The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.