SiC MOSFET Gate Insulator Interface Engineering
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Solution Overview
Problem
The challenge in forming silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs is the degradation of carrier mobility due to a high density of interface states between the SiC layer and the silicon oxide gate insulating layer, which also leads to threshold voltage fluctuation.
Innovation Solution
Incorporating a silicon oxide layer with elements like phosphorus, arsenic, antimony, or bismuth, where at least part of these elements are single bonded to three oxygen atoms and double bonded to one oxygen atom, which acts as a termination element to reduce interface states and intra-gap states in the gate insulating layer, thereby improving carrier mobility and threshold voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a silicon oxide layer is used as a gate insulating layer in SiC MOSFET, then the device can operate at high temperature with high breakdown field strength, but carrier mobility is lowered due to high density of interface states
Solution Approach 1:
The patent applies local quality by creating a graded interface structure between the SiC layer and silicon oxide layer. Specifically, a silicon-rich region is formed at the interface with a concentration gradient, where the silicon concentration is highest at the interface and decreases toward the bulk SiC layer. This localized modification of composition at the critical interface region reduces interface states while maintaining the overall properties of both materials, thereby improving carrier mobility without sacrificing the high temperature operation capability provided by the silicon oxide gate insulating layer.
2Strength
If a metal oxide semiconductor field effect transistor is formed using SiC, then high breakdown field strength and thermal conductivity are achieved, but threshold voltage fluctuation occurs due to interface states
Solution Approach 1:
The patent applies local quality by creating a graded interface structure between the SiC layer and silicon oxide layer. Specifically, a silicon-rich region is formed at the interface with a concentration gradient, where the silicon concentration is highest at the interface and decreases toward the bulk SiC layer. This localized modification of composition at the critical interface region reduces interface states while maintaining the overall properties of both materials, thereby improving carrier mobility without sacrificing the high temperature operation capability provided by the silicon oxide gate insulating layer.
Data Source
AI summary
A semiconductor device according to the embodiments described herein includes a silicon carbide layer and a silicon oxide layer. The silicon oxide layer is disposed on the silicon carbide layer and contains at least one element selected from a group of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). In the silicon oxide layer, at least a part of the at least one element is single bonded to three oxygen atoms and double bonded to one oxygen atom.