SiC MOSFET Gate Layout for Lower Internal Gate Resistance
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Solution Overview
Problem
The high internal gate resistance of silicon carbide MOSFETs limits their performance and requires higher external gate resistance in parallel connections, which can lead to unbalanced switching and increased switching loss, necessitating a reduction in internal gate resistance for improved efficiency and cost-effectiveness.
Innovation Solution
The design of a silicon carbide MOS-gated semiconductor device with a gate bus region comprising a single gate pad area and staggered, alternating gate electrode openings, which reduces the internal gate resistance by optimizing the layout and structure of the gate electrode and doped regions, allowing for adjustable gate resistance based on the position of the gate pad relative to the active region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the chip size of SiC MOSFET is reduced to achieve lower on-resistance, then the on-resistance is improved, but the internal gate resistance increases
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode portion, second gate electrode portion, third gate electrode portion) arranged in a staggered pattern. This segmentation allows current to flow through multiple parallel paths, effectively reducing the internal gate resistance while maintaining a compact chip size.
Solution Approach 2:
The gate electrode portions are arranged in a three-dimensional staggered configuration rather than a simple planar layout. This spatial arrangement creates multiple current flow paths through the drift layer, reducing resistance without increasing the chip's footprint area.
2Power
If multiple MOSFETs are connected in parallel to achieve higher power level, then the power level is improved, but the switching balance deteriorates due to higher internal gate resistance
Solution Approach 1:
The segmented gate electrode structure provides multiple parallel current paths that can be distributed across multiple MOSFETs in a parallel connection. This segmentation ensures more uniform current distribution and reduces the impact of internal gate resistance variations, improving switching balance in parallel configurations.
Data Source
AI summary
A silicon carbide MOS-gated semiconductor device comprises a silicon carbide substrate, a drift layer, a first doped region, a second doped region, a plurality of third doped regions, a gate insulating layer, a gate electrode, an interlayer dielectric layer, and a metal layer. The gate electrode comprises a gate bus region and an active region. The active region comprises a plurality of gate electrode openings. The two adjacent gate electrode openings have a minimum width (Wg) which is satisfied the following formula:Wg>Wjfet+2×Lch+2×Lx Lch represents a channel length of channel regions, Wjfet represents a minimum width of JFET regions, and Lx represents a minimum overlapping length between the gate electrode and the second doped region.