SiC MOSFET Gate Pad Reliability via Localized Carrier Recombination Control
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Solution Overview
Problem
In vertical SiC-MOSFETs, high electric potential applied to the source electrode leads to carrier concentration at the gate electrode pad, increasing conductivity modulation and generating crystal defects, which in turn increase ON resistance and vary the forward voltage and threshold voltage.
Innovation Solution
A semiconductor device structure with a lower carrier recombination rate in the gate pad region, achieved by reducing the impurity concentration of the p-type base layer to 10 times lower than the p+-type contact region and introducing a lifetime killer region, which reduces carrier recombination and crystal defect generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high electric potential is applied to the source electrode, then the built-in PN diode can be driven, but carrier concentration occurs at the gate electrode pad, increasing conductivity modulation and generating crystal defects
Solution Approach 1:
The patent applies local quality by creating a dedicated lower region beneath the gate electrode pad with distinct properties (lower impurity concentration, lower carrier recombination rate) compared to other regions. This localized structural modification allows the region to specifically address carrier concentration issues without affecting the overall device function, thereby resolving the contradiction between driving capability and reliability.
2Quantity of substance
If carrier concentration occurs at the gate electrode pad, then conductivity modulation increases, but ON resistance increases and threshold voltage varies
Solution Approach 1:
The patent changes the parameter of impurity concentration in the dedicated lower region, setting it to be lower than in other regions. This parameter change results in a lower carrier recombination rate, which stabilizes the threshold voltage and reduces ON resistance by preventing excessive carrier concentration at the gate electrode pad, thus resolving the contradiction between carrier concentration and voltage stability.
3Reliability
If the impurity concentration of the p-type base layer is reduced to 10 times lower than the p+-type contact region, then carrier recombination rate decreases, but device complexity increases
Solution Approach 1:
The patent segments the device structure by creating a dedicated lower region with distinct impurity concentration characteristics, separate from the rest of the device. This segmentation allows independent optimization of the region's properties to control carrier recombination without requiring complex modifications throughout the entire device, thereby resolving the contradiction between reliability improvement and device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure decreases current concentration and conductivity modulation in the gate pad region, thereby reducing ON resistance and stabilizing the threshold and forward voltages, enhancing the reliability of the semiconductor device.
Implementation Method 1
A first lower region, opposing the gate electrode pad in a depth direction, has a lower carrier recombination rate than a second lower region, opposing the first electrode in the depth direction
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate electrode, a first electrode, and a gate electrode pad. A first lower region opposing the gate electrode pad in a depth direction has a carrier recombination rate that is lower than that of a second lower region opposing the first electrode in the depth direction. With such a configuration, when high electric potential is applied to a source electrode and a built-in PN diode is driven, the generation of crystal defects may be suppressed.