SiC MOSFET Gate Oxide Protection via P-type Buffer Layer
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Solution Overview
Problem
Silicon carbide (SiC) semiconductor devices face a reliability issue due to destruction of the gate oxide film when high voltage is applied, as the critical electric field exceeds the material limits, leading to increased electric field load on the oxide film, which is not addressed in existing silicon-based power devices.
Innovation Solution
A silicon carbide semiconductor device structure is developed with a first-conductivity-type semiconductor substrate and a second-conductivity-type semiconductor layer, where the source region is formed under the gate pad, and the crystallographic plane index is tilted relative to the (0001) plane, reducing the electric field on the gate oxide film and maintaining low ON-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high voltage is applied to SiC semiconductor devices, then breakdown voltage is improved, but the gate oxide film is destroyed due to excessive electric field
Solution Approach 1:
A P-type semiconductor layer is introduced as an intermediary between the N-type drift layer and the gate oxide film. This P-type layer acts as a buffer that reduces the electric field intensity at the gate oxide interface, preventing film destruction while allowing high breakdown voltage operation. The intermediary layer effectively mediates the conflict between high voltage requirements and gate oxide protection.
Solution Approach 2:
The invention changes the electrical parameters of the semiconductor structure by introducing a P-type layer with specific doping concentrations (1×10^16 to 1×10^18 atoms/cm³) and thickness (0.1 to 10 μm). This parameter modification creates a controlled electric field distribution that reduces peak field intensity at the gate oxide interface, enabling high breakdown voltage without compromising gate oxide integrity.
2Power
If the critical electric field of SiC is utilized, then power handling capability is improved, but the electric field load on the oxide film exceeds material limits
Solution Approach 1:
The P-type semiconductor layer serves as a protective intermediary that shields the gate oxide film from the high electric field loads generated by SiC's superior power handling capabilities. This intermediary structure allows the device to utilize SiC's high critical electric field (10-fold greater than silicon) while preventing excessive field intensity from reaching the gate oxide.
Solution Approach 2:
The invention applies local quality modification by creating a P-type layer with specific doping characteristics in the region adjacent to the gate oxide film. This localized structural modification ensures that the area most vulnerable to electric field damage (the gate oxide interface) is protected, while the bulk SiC material maintains its high power handling capabilities elsewhere in the device.
Data Source
AI summary
A silicon carbide semiconductor device has a first-conductivity-type semiconductor layer having a lower impurity concentration and formed on a first-conductivity-type semiconductor substrate, a second-conductivity-type semiconductor layer having a higher impurity concentration and selectively formed in the first-conductivity-type semiconductor layer, a second-conductivity-type base layer having a lower impurity concentration formed on a surface of the second-conductivity-type semiconductor layer, a first-conductivity-type source region selectively formed in a surface layer of the base layer, a first-conductivity-type well region formed to penetrate the base layer from a surface to the first-conductivity-type semiconductor layer, and a gate electrode formed via a gate insulation film on a surface of the base layer interposed between the source region and the well region. Portions of the respective second-conductivity-type semiconductor layers of different cells can be connected to each other by a connecting portion in a region under the well region.