SiC MOSFET Gate Electrode Relocation for Dielectric Breakdown Prevention

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Solution Overview

Problem

Conventional vertical MOSFETs face dielectric breakdown and reliability issues with the gate insulation film when high voltage is applied, particularly due to the difference in dielectric breakdown electric fields between SiC and SiO2, leading to potential damage from avalanche breakdown.

Innovation Solution

The semiconductor device design excludes the base layer surface as the gate electrode arrangement position, placing the gate electrode only on the surface of the P-type region, thereby avoiding high electric fields on the gate insulation film and reducing the risk of dielectric breakdown, while maintaining the original MOSFET function.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the gate electrode is formed on the base layer surface in conventional MOSFETs, then the MOSFET switching function is achieved, but the gate insulation film suffers dielectric breakdown under high voltage due to avalanche breakdown in SiC

Engineering Contradiction:
Improvegate insulation film reliabilityVSAvoidhigh electric field damage to gate insulation film
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The invention extracts the gate electrode from the base layer surface area and relocates it exclusively to the P-type region surface. This separation removes the gate electrode's interaction with the base layer surface, preventing the high electric field from forming across the gate insulation film during avalanche breakdown, thereby eliminating the dielectric breakdown issue while preserving MOSFET functionality

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The P-type region acts as an intermediary layer between the gate electrode and the base layer. By positioning the gate electrode on the P-type region surface rather than directly on the base layer, the structure mediates the electric field distribution, allowing the gate to control the channel without being directly exposed to the high electric fields that cause avalanche breakdown in the base layer

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the dielectric breakdown and reliability of the gate insulation film by preventing high electric fields from forming when the gate voltage is applied, thus improving the overall performance of the MOSFET.

Implementation Method 1

the formation of an inversion layer on the surface of the P-type region 3 (see FIG. 10) or the surface of the P-type SiC layer 11 (see FIG. 11) immediately below the gate electrode 7 causes current to flow

Methodology Applied
Scientific EffectInversion layer formation:

Implementation Method 2

PN-junction between the P-type region 3 and the N-type SiC layer 2 (see FIG. 10) or PN-junction between the P-type SiC layer 11 and the N-type region 12 (see FIG. 11) is inversely-biased and therefore, no current flows

Methodology Applied
Scientific EffectPN-junction reverse bias:

Implementation Method 3

the dielectric breakdown electric field of 4H-SiC is 2.8×10^6 V/cm, which is higher than 1×10^6 V/cm for SiO2, and therefore, when the applied voltage is divided between SiC and SiO2 (withstand voltage), a problem arises in that before the SiC starts avalanche breakdown (reach the dielectric breakdown electric field), the SiO2 breaks down

Methodology Applied
Scientific EffectDielectric breakdown resistance: Dielectric

Implementation Method 4

before the SiC starts avalanche breakdown (reach the dielectric breakdown electric field), the SiO2 breaks down

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS9537002B2Semiconductor device with SiC base layer
Publication Date: 2017.01.03 FUJI ELECTRIC CO LTD
  • US9537002B2 patent drawing
  • US9537002B2 patent drawing
  • US9537002B2 patent drawing

AI summary

A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode.