Shielded SiC Power MOSFET Layout for Gate Oxide Field Reduction
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Solution Overview
Problem
MOSFET transistors, particularly power MOSFETs made from silicon carbide, face issues with elevated electric fields at the gate oxide interface, leading to potential oxide deterioration and device failure due to high voltage operation.
Innovation Solution
A semiconductor device design with a shielding region located below the JFET region between well regions, connected to the source terminal, reduces the electric field near the gate oxide interface by using a second-conductivity-type shield region with higher dopant concentration, ensuring electrical connection to the source potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage operation is used to increase power capability, then power capability is improved, but electric field at gate oxide interface increases causing oxide deterioration
Solution Approach 1:
A shielding region of second conductivity type is introduced as an intermediary structure between the gate oxide interface and the high voltage field. This shielding region, positioned in the drift region below the JFET region, acts as a mediator that redistributes and reduces the electric field intensity at the critical gate oxide interface while allowing high voltage operation to continue in the drain region.
Solution Approach 2:
The patent applies local quality by creating a shielding region with specific doping characteristics (second conductivity type, higher dopant concentration) in a localized area below the JFET region. This localized modification of electrical properties in the drift region provides field reduction precisely where needed near the gate oxide interface, while maintaining high voltage capability in other regions of the device.
2Object-affected harmful factors
If shielding region is positioned at gate insulator interface or within JFET region, then electric field shielding is achieved, but device complexity increases due to additional processing steps
Solution Approach 1:
The shielding region is formed preliminarily during the standard device fabrication sequence, specifically by performing a doping step (such as ion implantation or in-diffusion) at an appropriate stage before final device assembly. This preliminary formation of the shielding region integrates the field-reduction function into the existing manufacturing flow without requiring separate, complex processing equipment or steps.
Solution Approach 2:
The patent merges the shielding region formation with existing device fabrication steps. The doping process that creates the shielding region is combined with or integrated into the standard sequence of well formation, JFET region creation, and contact formation steps, thereby achieving dual functionality (device structure + field shielding) through unified processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates the risk of gate oxide deterioration by shielding the gate from high electric fields, enhancing the reliability and performance of MOSFET transistors under high voltage conditions.
Implementation Method 1
elevated electric fields at the gate oxide interface
Implementation Method 2
shielding region located below the JFET region between well regions, connected to the source terminal, reduces the electric field near the gate oxide interface
Data Source
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AI summary
The present disclosure relates to a semiconductor device and a method of manufacturing semiconductor device. The present disclosure relates particularly to MOSFET transistors. A semiconductor device according to the disclosure comprising: a first-conductivity-type substrate, a first-conductivity-type epitaxy layer comprising a JFET region and a second-conductivity-type shield region, two well regions comprising two source regions, gate oxide comprising a gate, a drain adjacent to the first-conductivity-type substrate, wherein the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, wherein the two well regions are adjacent to the first-conductivity-type epitaxy layer, wherein the JFET region is located between the two well regions, wherein the source contact region is the outermost layer and is adjacent to the two source regions, wherein the gate oxide is adjacent to the two well regions, the two source regions, and the JFET region.