SiC Vertical MOSFET Gate Structure Without Metal Bias Rings
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Solution Overview
Problem
Existing vertical-conduction silicon carbide MOSFET devices face challenges due to the presence of gate metal fingers and rings, which complicate power module designs, increase costs, and reduce reliability, especially in high-humidity environments.
Innovation Solution
The proposed solution involves a vertical-conduction MOSFET device with a simplified gate biasing structure that eliminates the need for gate metal fingers and rings, utilizing an annular connection region formed monolithically with the gate conductive regions to provide improved gate resistance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional lateral-conduction SiC MOSFET structure is used, then manufacturing process is simpler, but device breakdown voltage is limited and on-resistance is high
Solution Approach 1:
The patent transitions from lateral-conduction to vertical-conduction architecture, changing the current flow direction from horizontal to vertical through the semiconductor substrate. This dimensional change enables higher breakdown voltage and lower on-resistance by utilizing the vertical field effect transistor structure where the electric field is distributed vertically through the drift region rather than laterally at the surface.
Solution Approach 2:
The patent implements a multi-layer gate structure where a first gate electrode and second gate electrode are stacked vertically, with the second gate positioned over the first gate. This nested arrangement allows independent control of different gate regions to manage electric field distribution and prevent premature breakdown at the drain junction, enabling higher voltage operation.
2Productivity
If vertical-conduction SiC MOSFET with multi-layer gate is implemented, then breakdown voltage increases and on-resistance decreases, but manufacturing complexity increases
Solution Approach 1:
The gate structure is segmented into multiple independent gate electrodes (first gate and second gate) that can be controlled separately. This segmentation allows optimization of each gate region for specific functions: the first gate controls the main channel while the second gate manages the drain junction electric field, enabling high voltage operation without requiring entirely new manufacturing processes.
Solution Approach 2:
The multi-layer gate structure serves multiple functions simultaneously: it provides voltage control for the MOSFET channel, manages electric field distribution at the drain junction, and enables higher breakdown voltage operation. This multi-functionality is achieved within an extended CMOS-compatible process framework rather than requiring completely new manufacturing techniques.
3Reliability
If gate biasing structure is added to control electric field distribution, then premature breakdown is prevented, but device complexity increases
Solution Approach 1:
The second gate electrode acts as an intermediary element between the control circuitry and the drain junction electric field. By applying appropriate bias to the second gate, the electric field distribution at the drain junction can be controlled to prevent premature breakdown, while the first gate maintains normal channel operation. This intermediary structure enables reliable high-voltage operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the active area utilization, improves gate resistance, and increases the robustness of the MOSFET device, allowing it to operate effectively in high-current and high-voltage applications with improved reliability and reduced manufacturing costs.
Implementation Method 1
a self-aligned n-type extension region is formed by selective epitaxial growth
Implementation Method 2
a portion of the drift region is subjected to ion implantation
Implementation Method 3
a plurality of recess regions are formed by selectively removing portions of the semiconductor substrate
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A vertical-conduction MOSFET device (50) formed in a body (55) of silicon carbide having a first and a second face (52A, 52B) and a peripheral zone (87). A drain region (57), of a first conductivity type, extends in the body (55) between the two faces. A body region (60), of a second conductivity type, extends in the body from the first face (55A), and a source region (65), having the first conductivity type, extends to the inside of the body region (60) from the first face (55A) of the body. An insulated gate region (70) extends on the first face of the body and comprises a gate conductive region (72). An annular connection region (86), of conductive material, is formed within a surface edge structure extending on the first face (55A) of the body (55), in the peripheral zone (87). The gate conductive region (72) and the annular connection region (86) are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.