SiC MOSFET Hexagonal Cell Design Reduces On-Resistance
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Solution Overview
Problem
SiC MOSFET devices have a high specific on-resistance, which leads to increased conduction power loss due to the significant channel resistance component, primarily attributed to poor inversion layer mobility and the 'overhead' parameters in the stripe geometry design, limiting their performance in high-voltage power electronic applications.
Innovation Solution
The proposed semiconductor device structure features a ring-circumscribing JFET region with strategically positioned well and source regions, eliminating the polysilicon gate to silicide contact spacing and gate overlap, allowing for a continuous polysilicon gate and reducing the cell pitch, thereby increasing channel width and minimizing the channel resistance component. Additionally, the integration of a Schottky diode reduces reverse conduction losses and enhances stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a conventional stripe geometry design is used, then the device structure is simple, but the channel width per active area is limited and channel resistance is high
Solution Approach 1:
The patent transitions from a conventional one-dimensional stripe geometry to a two-dimensional hexagonal cell geometry. This dimensional change allows the channel to extend in multiple directions (X and Y directions) rather than just one direction, thereby increasing the effective channel width per unit active area and reducing channel resistance without simply scaling up the device size.
Solution Approach 2:
The device is segmented into multiple hexagonal cells, each containing its own JFET region, well regions, and source regions. This segmentation allows for optimized current flow paths in each cell while maintaining a compact overall structure, increasing the channel width per active area through efficient spatial arrangement.
2Length of moving object
If polysilicon gate to silicide contact spacing and gate overlap are included, then the design follows conventional practices, but the cell pitch increases and channel width per active area decreases
Solution Approach 1:
The patent extracts and eliminates the conventional polysilicon gate to silicide contact spacing and gate overlap requirements from the design. By removing these non-functional spacing requirements, the cell pitch is reduced, allowing for a higher density of active channels per unit area and effectively increasing the channel width contribution to device performance.
Solution Approach 2:
Instead of following the conventional approach where gate spacing and overlap are added to ensure proper function, the patent inverts the approach by designing the gate structure to extend continuously over the channel without requiring additional spacing to silicide contacts. This inversion of the conventional design rule eliminates the overhead and optimizes the channel width to cell pitch ratio.
3Loss of energy
If traditional well and source region configurations are used, then the manufacturing process is straightforward, but the specific on-resistance remains high
Solution Approach 1:
The patent applies local quality by creating specific well regions (first and second well regions) with different configurations and doping levels in different locations within the hexagonal cell. The first well region has a first doping concentration while the second well region has a second doping concentration, allowing optimization of carrier flow and field distribution in different areas to reduce overall on-resistance.
Solution Approach 2:
The device structure combines multiple semiconductor materials and doping configurations within the same device - including the drift layer, multiple well regions with different doping concentrations, and source regions - creating a composite structure that optimizes both conduction and blocking properties to reduce specific on-resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a 2x increase in channel width per active area, significantly reducing the specific on-resistance and overall on-state resistance of the DMOSFET, while also improving robustness to voltage transients and eliminating the need for external Schottky rectifiers, thus enhancing the performance and reliability of SiC MOSFET devices.
Implementation Method 1
the integration of a Schottky diode reduces reverse conduction losses and enhances stability
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described