SiC MOSFET Source Interconnection Cavity Prevention
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Solution Overview
Problem
Silicon carbide MOSFETs experience reliability issues due to cavity formation in thick source electrode interconnections, which can break under high current flow, reducing electromigration resistance.
Innovation Solution
The method involves forming interlayer insulating films with reduced level differences by heating and using multiple insulating layers with varying softening points, along with isotropic and anisotropic etching techniques to create recesses that enhance adhesion and prevent cavity formation, and using titanium and titanium nitride metal layers for improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a thick source electrode interconnection is formed to handle larger current in silicon carbide MOSFET, then current carrying capacity is improved, but cavity formation occurs inside the interconnection near corner portions, reducing reliability
Solution Approach 1:
The patent performs preliminary actions by forming recesses in the interlayer insulating film before depositing the thick source electrode interconnection. These recesses are strategically positioned at corner portions where cavities are most likely to form during subsequent processing. By preparing the surface topology in advance, the patent prevents cavity formation rather than attempting to repair it later, allowing the thick interconnection to be formed with improved current carrying capacity while maintaining reliability.
Solution Approach 2:
The patent introduces curvature by forming recesses with rounded bottom surfaces instead of sharp corners. This spherical/curved geometry at the recess bottoms prevents stress concentration and provides a favorable surface for metal deposition, eliminating the corner portions where cavities typically nucleate during thick interconnection formation. The curved surfaces promote uniform metal adhesion and prevent void formation while maintaining the necessary interconnection thickness for high current applications.
2Shape
If the insulating film is formed along the shape of the gate insulating film to surround the gate electrode, then gate electrode coverage is improved, but corner portions are formed in the insulating film, leading to cavity formation in thick interconnections
Solution Approach 1:
The patent segments the insulating film formation process into multiple stages: first forming the gate insulating film, then forming an additional insulating film that extends beyond the gate electrode corners. This segmentation allows the insulating film to provide both gate coverage and extended corner protection. The additional insulating material fills the corner regions created by the gate electrode geometry, preventing cavity formation in the overlying thick source electrode interconnection while maintaining proper gate electrode coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses cavity formation and enhances the reliability of interconnections by improving adhesion and reducing the risk of interconnection breakdown under high current conditions.
Implementation Method 1
the step of reducing a level difference in an upper surface of the interlayer insulating film by heating the interlayer insulating film
Implementation Method 2
Where the deposited oxide layer is rich in phosphorus, a wet etchant is used to etch through the deposited oxide layer
Implementation Method 3
Then a plasma etchant is used to form an opening through the thermally grown oxide
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A silicon carbide substrate (10) having a gate insulating film (20) provided in contact with a first main surface (10a), having a gate electrode (30) provided in contact with the gate insulating film (20), and having a source region (15) exposed from first main surface (10a) is prepared. A first recess (46) having a first inner wall surface (46a) is formed in an interlayer insulating film (40) by performing a first isotropic etching with respect to the interlayer insulating film (40) with use of a mask layer (45). A second recess (47) having a second inner wall surface (47a) is formed by performing a first anisotropic etching with respect to the interlayer insulating film (40) and the gate insulating film (20) with use of the mask layer (45) and thereby exposing the source region (15) from gate insulating film (20). An interconnection (60) is formed which is arranged in contact with the first inner wall surface (46a) and the second inner wall surface (47a) and electrically connected to a source electrode (50). Accordingly, a silicon carbide semiconductor device capable of improving the reliability of the interconnection and a method for manufacturing the silicon carbide semiconductor device can be provided.