SiC Vertical MOSFET Gate Structure With Inter-Gate Plates
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Solution Overview
Problem
Silicon carbide (SiC) based MOSFETs face challenges in high power applications due to lower internal gate-source capacitance (C GS) compared to silicon-based MOSFETs, leading to erroneous turn-on during transients, necessitating a space-efficient method to enhance C GS.
Innovation Solution
The introduction of inter-gate plates that overlap the source/emitter implant and are separated by a gate dielectric in a vertical FET structure, providing additional internal capacitance, which can be formed from the same or different materials as the gate contacts, within the epitaxial structure of silicon carbide or other material systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC-based MOSFET structure is used, then high power application capability is achieved, but gate-source capacitance is insufficient leading to erroneous turn-on
Solution Approach 1:
The patent embeds inter-gate plates within the gate structure itself, nesting additional capacitive elements inside the existing device footprint. The inter-gate plates are positioned between the gate electrode and the drain region, creating nested capacitive coupling that increases gate-source capacitance without requiring external components or increasing device area.
Solution Approach 2:
The patent introduces a vertical dimension to the gate structure by extending inter-gate plates in the vertical direction between the gate electrode and drain. This vertical stacking creates additional capacitance pathways in the third dimension, increasing gate-source capacitance without expanding the horizontal device footprint.
2Reliability
If device area is increased to enhance capacitance, then gate-source capacitance increases, but module size increases
Solution Approach 1:
The inter-gate plates are nested within the existing gate structure boundaries, utilizing the vertical space between the gate electrode and drain region. This nesting approach adds capacitance functionality without requiring additional horizontal space, maintaining the original device footprint while enhancing electrical characteristics.
Solution Approach 2:
By transitioning to vertical stacking of inter-gate plates between the gate and drain, the patent exploits the vertical dimension to increase capacitance. This dimensional transition allows significant capacitance enhancement while keeping the horizontal device area constant, thus preventing module size increase.
3Speed
If Miller capacitance is reduced, then switching speed improves, but susceptibility to transient-induced turn-on increases
Solution Approach 1:
The patent selectively modifies the capacitance parameters of the device by introducing inter-gate plates that specifically increase gate-source capacitance while maintaining or reducing Miller capacitance. This parameter differentiation allows the device to achieve both fast switching (low Miller capacitance) and transient immunity (high gate-source capacitance) simultaneously.
Solution Approach 2:
The inter-gate plates are strategically positioned to create localized capacitive coupling specifically between the gate and source regions. This local quality enhancement increases gate-source capacitance in the critical region without affecting other parts of the device, allowing selective improvement of transient immunity while preserving switching performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases the gate-source to gate-drain capacitance ratio, effectively suppressing erroneous turn-on events during high-speed turn-offs without increasing the module size, allowing SiC-based MOSFETs to compete with silicon-based devices in terms of performance.
Implementation Method 1
Additional internal capacitance is provided where each of the first plurality of inter-gate plates overlap a portion of the first source/emitter implant and the inter-gate plates are separated by the gate dielectric
Data Source
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AI summary
A vertical FET includes a silicon carbide substrate having a top surface and a bottom surface opposite the top surface; a drain/collector contact on the bottom surface of the silicon carbide substrate; and an epitaxial structure on the top surface of the silicon carbide substrate having formed therein a first source/emitter implant. A gate dielectric is provided on a portion of the epitaxial structure. First source/emitter contact segments are spaced apart from each other on the first source/emitter implant. A first and second elongated gate contact are on the gate dielectric and positioned such that the first source/emitter implant is below and between the first elongated gate contact and the second elongated gate contact. Inter-gate plates extend from at least one of the first elongated gate contact and the second elongated gate contact into spaces formed between the first source/emitter contact segments.