SiC MOSFET Cell Array Embedded with Junction Barrier Schottky Diode
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Solution Overview
Problem
Conventional Si-based power devices face challenges with high thermal resistivity, large heat sink modules, and high switching energy loss, which are addressed by using SiC devices, but the conventional fabrication method of separate MOSFET and JBS diode chips leads to increased space and production costs due to numerous wirings and stray inductance.
Innovation Solution
An integrated device with a metal oxide semiconductor field effect transistor (MOSFET) cell array embedded with a junction barrier Schottky (JBS) diode, where the JBS diode is connected in anti-parallel to the MOS transistor cells and disposed at intersection regions, reducing the need for separate chips and wirings, thus minimizing space and production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOSFET and JBS diode are fabricated on separate chips and packaged together, then device functionality is achieved, but the number of wirings increases and stray inductance increases
Solution Approach 1:
The patent merges the MOSFET and JBS diode onto a single SiC substrate, integrating both devices into one chip. This eliminates the need for separate chips and their associated wirings, directly reducing stray inductance and simplifying the overall device structure while maintaining full functionality of both components
2Reliability
If MOSFET and JBS diode are fabricated on separate chips and packaged together, then device functionality is achieved, but space requirements and production costs increase
Solution Approach 1:
By combining both the MOSFET and JBS diode on a single integrated chip, the patent significantly reduces the total space required compared to housing two separate chips with their respective packaging and connections. This integration approach minimizes the footprint while preserving all necessary device functions
3Adaptability or versatility
If Si-based devices are used, then device compatibility is maintained, but thermal resistivity is high and heat dissipation becomes problematic
Solution Approach 1:
The patent changes the material parameter from silicon-based to silicon carbide (SiC), which fundamentally alters the thermal properties. SiC has approximately three times the thermal conductivity of silicon, enabling superior heat dissipation while maintaining the necessary electrical and functional characteristics for power device applications
4Adaptability or versatility
If Si-based devices are used, then device compatibility is maintained, but switching energy loss increases
Solution Approach 1:
By transitioning from silicon to silicon carbide material, the patent achieves faster switching speeds and lower switching energy loss. The wider bandgap of SiC enables higher critical breakdown fields and faster carrier depletion, dramatically reducing switching losses while maintaining compatibility with existing power device architectures and applications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated device reduces production costs and space requirements while enhancing switching speed and efficiency by eliminating the need for separate chip packaging, leading to lower power consumption and improved thermal management.
Implementation Method 1
a junction barrier Schottky (JBS) diode... The at least one JBS diode is disposed at an intersection region between the first separating line and the second separating line, wherein the JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells
Data Source
AI summary
Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a plurality of MOS transistor cells and at least one JBS diode. Any two adjacent MOS transistor cells are separated by a separating line. A first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line. The JBS diode is disposed at an intersection region between the first separating line and the second separating line. The JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells.