SiC MOSFET JFET Doping Layout for Gate Oxide Field Relief

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Solution Overview

Problem

Silicon carbide MOSFET devices face reliability issues due to high electrical fields at the interfaces between silicon oxide and silicon carbide, leading to dielectric breakdown, which existing solutions like increasing epitaxial layer thickness or reducing doping concentrations undesirably increase on-resistance and manufacturing costs.

Innovation Solution

Incorporating modified-doping regions with reduced dopant concentration in the JFET regions of the MOSFET device, formed through localized implantation or epitaxial growth, to reduce electrical fields without altering breakdown characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the thickness of the epitaxial layer is increased to reduce the electrical field at the SiO2-SiC interface, then the reliability is improved, but the on-resistance increases

Engineering Contradiction:
ImprovereliabilityVSAvoidon-resistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent introduces modified-doping regions with reduced dopant concentration specifically in the surface-separation regions (JFET regions) underneath the gate structures, while maintaining the original dopant concentration in other regions. This localized modification reduces the electrical field at the SiO2-SiC interface in critical areas without increasing the on-resistance of the entire device, thereby resolving the contradiction between reliability and energy loss.

Inventive Principle:
Principle #3Local quality

2Reliability

If the doping concentration in the epitaxial layer is reduced to reduce the electrical field, then the reliability is improved, but the breakdown voltage decreases

Engineering Contradiction:
ImprovereliabilityVSAvoidbreakdown voltage
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent applies modified-doping regions only in specific surface-separation regions underneath gate structures, while maintaining the original dopant concentration in the bulk epitaxial layer and other critical regions. This localized approach reduces the electrical field at the SiO2-SiC interface in areas where it causes reliability issues, without compromising the overall breakdown voltage of the device.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modifies the doping concentration in the lateral dimension (surface-separation regions) rather than uniformly reducing it throughout the vertical dimension. This dimensional specificity allows field reduction at the interface without affecting the vertical breakdown characteristics of the drift layer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If the distance between adjacent body wells is reduced to reduce the electrical field, then the reliability is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
ImprovereliabilityVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the dopant concentration parameter in specific regions (surface-separation regions) to reduce the electrical field. This parameter modification achieves field reduction without requiring changes to the physical dimensions or spacing of body wells, thereby avoiding increased manufacturing precision requirements.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Effectively reduces electrical fields in the gate dielectric regions, enhancing reliability and maintaining breakdown voltage and threshold voltage values, while minimizing on-state resistance.

Implementation Method 1

reliability problems are linked to high electrical fields developing at the interfaces between silicon oxide (SiO2) and silicon carbide (4H-SiC)

Methodology Applied
Scientific EffectElectrical field: Electric Field

Implementation Method 2

modified-doping regions (40), arranged in the surface-separation regions (29) of said functional layer (24), underneath respective gate structures (30); said modified-doping regions (40) having a modified concentration of dopant as compared to the concentration of said functional layer (24)

Methodology Applied
Scientific EffectDopant concentration: Dopants

Data Source

PatentUS12622020B2Silicon carbide MOSFET transistor device with improved characteristics and corresponding manufacturing process
Publication Date: 2026.05.05 STMICROELECTRONICS SRL
  • US12622020B2 patent drawing
  • US12622020B2 patent drawing
  • US12622020B2 patent drawing

AI summary

A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.