SiC Power MOSFET JFET Layout for Gate Oxide Field Shielding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
MOSFET transistors, particularly power MOSFETs made from silicon carbide, face the challenge of elevated electric fields at the gate oxide interface, which can lead to oxide deterioration or destruction, rendering the device unusable.
Innovation Solution
The semiconductor device incorporates a JFET region with a width that is greater near the top surface than at the bottom, and second well regions with a notch at the bottom part toward the JFET region, creating a shielding effect for the gate interface. This is achieved through a manufacturing process involving epitaxy layers, scatter oxide layers, and angled dopant implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional MOSFET structure with uniform channel width is used, then the device can be manufactured with simple processes, but the electric field at the gate oxide interface becomes too large causing oxide deterioration
Solution Approach 1:
The channel region is segmented into multiple sections with different widths along its length. The channel has a wider section near the drain and a narrower section near the source, creating distinct functional zones that manage electric field distribution differently in each region, thereby protecting the gate oxide from excessive electric field stress.
Solution Approach 2:
Different regions of the channel are given different local properties through varying widths. The wider channel section near the drain provides lower resistance for high current flow, while the narrower section near the source reduces electric field concentration at the gate oxide interface, optimizing both conductivity and reliability locally.
2Use of energy by moving object
If the channel width is reduced to lower on-resistance, then conductivity improves, but the withstand voltage decreases
Solution Approach 1:
The channel width is made dynamic rather than uniform, varying continuously or in steps from source to drain. This dynamic geometry allows the channel to provide low resistance where high current flows (near drain) while maintaining adequate breakdown voltage where the electric field is most stressful (near source), achieving both low on-resistance and high withstand voltage.
Solution Approach 2:
Instead of changing channel width in the horizontal plane only, the invention introduces a longitudinal dimension variation, making the channel width a function of position along the channel length. This dimensional approach creates a gradient structure that simultaneously optimizes for both conductivity and voltage blocking capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the electric field near the gate oxide interface, thereby preventing oxide deterioration and enhancing the reliability and performance of the MOSFET transistors.
Implementation Method 1
The dopant is introduced into the regions by depositing a scatter oxide layer onto the first-conductivity-type epitaxy layer, creating a first mask on the scatter oxide layer, and implanting a dopant through the first mask at an angle
Implementation Method 2
a first-conductivity-type epitaxy layer
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present disclosure relates to a semiconductor device and a method of manufacturing semiconductor device. The present disclosure relates particularly to MOSFET transistors. A semiconductor device comprising a first-conductivity-type substrate, a first-conductivity-type epitaxy layer comprising a JFET region, two first well regions comprising two source regions, two second well regions, a scatter oxide layer, wherein the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, wherein the two first well regions are adjacent to the first-conductivity-type epitaxy layer and each of the two first well regions is adjacent to one second well region, wherein the JFET region is adjacent to the two second well regions, wherein the scatter oxide layer is adjacent to the two source regions, the two first well regions (8), the two second well region and the JFET region, wherein a width of the JFET region is greater near the scatter oxide layer than in part closest to the first-conductivity-type substrate.