SiC MOSFET JFET Layout With Diagonal Shielding Regions
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Solution Overview
Problem
SiC-based MOSFET devices face reliability issues due to high electric field stress on the gate oxide layer, leading to premature breakdown, especially when the JFET region is widened to enhance current flow, which increases on-resistance and compromises device reliability.
Innovation Solution
Incorporating shielding regions within the JFET region, connected to well regions and extending diagonally, to shield high electric field areas, while maintaining the current flow area of the JFET region, thereby reducing the electric field stress on the gate oxide layer and enhancing device reliability without additional manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of the JFET region is increased to achieve a larger current flow area, then the on-resistance decreases, but the voltage on the gate oxide layer increases causing premature breakdown and reduced reliability
Solution Approach 1:
The patent introduces shielding regions as intermediary structures between the JFET region and the gate oxide layer. These shielding regions, doped with the same type as the drift region, act as mediators that redirect and distribute the electric field lines, preventing direct stress concentration on the gate oxide layer while allowing the JFET region to maintain its current-carrying function
Solution Approach 2:
The patent applies local quality by creating regions with different doping characteristics at specific locations. The shielding regions are doped with the same type as the drift region (opposite to JFET region doping), creating localized zones with distinct electrical properties that modify the electric field distribution only where needed, without altering the overall device structure
2Reliability
If the width of the JFET region is reduced to decrease on-resistance, then the gate oxide layer reliability improves, but the current carrying capacity of the device decreases
Solution Approach 1:
The shielding regions serve as intermediary structures that enable the JFET region to maintain an optimal width for current carrying while protecting the gate oxide layer. By introducing these intermediate doped regions, the device achieves both high current capacity and gate oxide reliability simultaneously
3Reliability
If shielding regions are added to protect the gate oxide layer, then device reliability improves, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of shielding regions with existing device structures. The shielding regions are created using the same ion implantation processes already employed for well regions and source regions, combining multiple functions into unified manufacturing steps rather than adding separate complex processes
Solution Approach 2:
The shielding regions serve multiple functions simultaneously: they protect the gate oxide layer from electric field stress, maintain the current carrying capacity of the JFET region, and are formed using standard ion implantation processes already part of the manufacturing workflow, thus achieving reliability improvement without proportionally increasing process complexity
Data Source
AI summary
A SiC-based MOSFET device and a method for manufacturing the same. Layout design of SiC-based MOSFET devices is optimized, which keeps the JFET region while introducing shielding regions extending into the JFET region, thereby retaining the current flow area of the JFET region to a great extent; each shielding region is connected to the respective well region and extends into the JFET region along a diagonal direction of the cellular structure, effectively shielding high electric field regions when the device is reverse biased, and significantly enhancing the device's reliability. The shielding regions and the well regions are simultaneously formed, requiring no additional process, avoiding increase in complexity and cost of manufacturing. This approach achieves low on-resistance and prevents a decrease in reliability caused by the electric field strength at the bottom of the gate oxide layer exceeding a critical breakdown electric field strength of the gate oxide layer.