SiC MOSFET Channel Structure for Leakage Current Blocking
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Solution Overview
Problem
Existing silicon carbide (SiC) MOSFETs face challenges in controlling channel thickness and doping concentration, leading to leakage current issues that affect electrical performance and reliability.
Innovation Solution
The proposed power semiconductor device includes a specific structure with a first well of a second conductivity type under a gate insulating layer, spaced apart from second wells, forming a channel with controlled thickness and width, and a PN junction at channel ends to prevent leakage current through depletion in the off-state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SiC MOSFET structures are used, then manufacturing is simpler, but channel thickness and doping concentration cannot be controlled, leading to leakage current
Solution Approach 1:
The device divides the channel region into multiple segments by introducing first and second wells of the second conductivity type at different depths. This segmentation allows independent control of channel thickness and doping concentration in different regions, solving the contradiction between manufacturing simplicity and channel control precision.
Solution Approach 2:
The patent applies local quality by creating regions with different doping concentrations (first conductivity type in channel, second conductivity type in wells) and different depths. The first well is positioned at a first depth while the second well is positioned at a second depth greater than the first depth, allowing localized control of electrical properties to prevent leakage current while maintaining overall device functionality.
2Reliability
If channel thickness is not controlled, then device structure is simpler, but leakage current occurs reducing electrical performance
Solution Approach 1:
The patent implements preliminary action by pre-forming the first and second wells at specific depths before final channel formation. This preliminary structuring establishes controlled doping regions that prevent leakage current before the channel is fully formed, improving reliability without excessive complexity.
Solution Approach 2:
The first and second wells act as intermediary structures between the source/drain regions and the channel. These intermediary doping regions control the electric field distribution and prevent leakage current by creating depletion regions, thereby improving electrical performance while maintaining manageable device complexity.
3Reliability
If doping concentration in channel is not controlled, then manufacturing is easier, but leakage current reduces device reliability
Solution Approach 1:
The doping structure is segmented into multiple regions with different concentrations and depths. The first well contains doping at a first concentration at a first depth, while the second well contains doping at a second concentration at a second depth. This segmentation allows independent optimization of each region's doping, improving reliability while keeping manufacturing feasible through standardized multi-step doping processes.
Solution Approach 2:
The patent changes multiple doping parameters independently: doping concentration (first vs second concentration), depth (first depth vs second depth), and spatial distribution (first well vs second well positions). By controlling these parameters separately, the invention achieves precise channel characteristics and leakage prevention while using conventional doping techniques, maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively controls channel width and thickness, reduces on-state resistance, and prevents leakage current, thereby enhancing electrical performance and reliability of SiC MOSFETs.
Implementation Method 1
when in the off state, a depletion is formed at the upper and lower portions to prevent the leakage current of the channel through channel blocking
Implementation Method 2
forms a PN junction at channel ends to prevent leakage current
Data Source
Figure 1
Figure 2~3
Figure 4A~4B
AI summary
A power semiconductor device according to an embodiment includes a substrate, an epi layer of a first conductivity type disposed on the substrate, a JFET region disposed on the epi layer of the first conductivity type, a plurality of second wells of a second conductivity type disposed spaced apart from each other in the JFET region, a source region of the first conductivity type disposed on the second wells of the second conductivity type, a gate insulating layer disposed on the source region of the first conductivity type, a gate disposed on the gate insulating layer, and a first well of the second conductivity type disposed under the gate insulating layer.