SiC MOSFET Well Formation Using Segmented Implantation Masks
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Solution Overview
Problem
The existing method for forming well regions in SiC power MOSFETs faces challenges in achieving high precision in photolithography, leading to difficulties in reducing the ON resistance due to thick implantation masks, which result in low degree of integration and increased channel resistance.
Innovation Solution
A method involving the reduction of the thickness of the implantation mask and the use of a self-aligning process to form source regions, enhancing photolithography controllability and precision, thereby miniaturizing well regions and improving unit cell integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick implantation mask is used to form well regions, then the mask provides sufficient coverage and protection, but photolithography precision deteriorates and unit cell integration is reduced
Solution Approach 1:
The implantation mask is divided into multiple thin layers instead of using a single thick mask. Each layer can be independently formed and controlled, allowing the total thickness to be sufficient for mask coverage while maintaining photolithography precision. The segmented structure enables better process control and reduces the negative effects of mask thickness on patterning accuracy.
2Reliability
If a thick implantation mask is used, then well region formation is achieved, but channel resistance increases due to reduced unit cell integration
Solution Approach 1:
The mask structure is segmented into multiple thin layers that can be precisely patterned, enabling better unit cell integration and reduced channel resistance while still achieving complete well region formation. The segmented approach allows for more accurate alignment and smaller cell pitches.
Solution Approach 2:
Instead of solving the thickness problem in a single dimension, the mask is constructed in multiple layers (adding vertical dimensionality), which allows the horizontal patterning precision to be improved while maintaining sufficient total mask thickness for proper well region formation.
3Ease of manufacture
If photolithography precision is reduced, then mask formation is simplified, but gate length reduction and ON resistance reduction become difficult
Solution Approach 1:
The mask is segmented into multiple thin layers that can be formed using standard photolithography processes, making mask formation easier while achieving high precision gate length control. Each thin layer can be precisely patterned with conventional equipment, avoiding the need for specialized high-precision processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the effective reduction of ON resistance by achieving good well contacts, reducing gate length, and enhancing unit cell integration, resulting in lower channel resistance and improved device performance.
Implementation Method 1
forming a well region of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer having the first mask formed thereon
Implementation Method 2
forming a second mask covering a portion of the well region by using photolithography
Data Source
AI summary
A production method for a semiconductor device includes providing a semiconductor substrate having semiconductor layer of a first conductivity type formed on a surface thereof; forming a first mask so as to cover a predetermined region of the semiconductor layer; (c) forming a well region of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer having the first mask formed thereon; reducing the thickness of the first mask by removing a portion of the first mask; forming a second mask covering a portion of the well region by using photolithography; and forming a source region of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer having the first mask with the reduced thickness and the second mask formed thereon.