SiC MOSFET n-type Region Optimization for Gate Reliability
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Solution Overview
Problem
The existing vertical MOSFETs on silicon carbide substrates face a trade-off between ON-resistance and breakdown voltage properties, with suboptimal impurity concentration and width of the n-type region leading to degraded gate insulating film reliability under high voltage applications.
Innovation Solution
A semiconductor device design with a specific impurity concentration and width range for the n-type region within the p-type SiC layer, optimizing ON-resistance and breakdown voltage, and enhancing the dielectric breakdown tolerance of the gate insulating film by controlling the impurity concentration and width of the n-type region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the impurity concentration and width of the n-type region are not optimized, then the device structure is simpler, but the ON-resistance and breakdown voltage properties cannot be simultaneously established in optimal states
Solution Approach 1:
The patent applies parameter changes by precisely controlling the impurity concentration (1.0×10^16 to 5.0×10^16 cm^-3) and width (0.8 μm to 3.0 μm) of the n-type region. This optimization resolves the technical contradiction by achieving both low ON-resistance and high breakdown voltage simultaneously, transforming the suboptimal device properties into excellent performance through specific parameter ranges.
2Ease of manufacture
If the width of the n-type region is not optimized, then the manufacturing process is simpler, but a high electric field is applied to the gate insulating film when high voltage is applied to the drain electrode
Solution Approach 1:
The patent resolves this contradiction by optimizing the width parameter of the n-type region to 0.8 μm to 3.0 μm. This specific width range reduces the electric field strength applied to the gate insulating film during high voltage operation, preventing dielectric breakdown while maintaining manufacturing feasibility through standard fabrication processes.
3Ease of manufacture
If the impurity concentration of the n-type region is not optimized, then the fabrication process is simpler, but the gate insulating film reliability is significantly degraded under high voltage conditions
Solution Approach 1:
The patent addresses this contradiction by establishing a specific impurity concentration range of 1.0×10^16 to 5.0×10^16 cm^-3 for the n-type region. This optimized concentration reduces the electric field stress on the gate insulating film during MOSFET operation, significantly improving dielectric breakdown tolerance and gate insulating film reliability while maintaining practical fabrication simplicity.
Data Source
AI summary
An n-type SiC layer is formed on a front face of an n+-type SiC substrate and plural p-type regions are selectively formed inside the n-type SiC layer. A p-type SiC layer is formed covering the surfaces of the n-type SiC layer and the p-type regions. An n-type region is formed inside the p-type SiC layer to be connected to the n-type SiC layer. An n+-type source region and a p+-type contact region are formed inside the p-type SiC layer, positioned away from the n-type region and in contact with each other. The n-type region in the p-type SiC layer is formed such that the width LJFET of the n-type region is within a range from 0.8 μm to 3.0 μm and the impurity concentration of the n-type region is greater than 1.0×1016 cm−3 and less than or equal to 5.0×1016 cm−3.