SiC MOSFET Gate Terminal Layout for Switching Oscillation Damping
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Solution Overview
Problem
SiC MOSFETs experience undesired voltage and current oscillations during switching due to their fast switching characteristics, leading to potential device damage, increased power losses, and electromagnetic interference, which limits their use in power electronics applications.
Innovation Solution
The electronic device incorporates a gate connection terminal that is capacitively coupled with the semiconductor body's edge termination region, increasing the gate-drain capacitance to dampen switching oscillations by providing additional feedback capacitance, thereby balancing the inverse recovery step of the body diode and reducing oscillation amplitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate-drain capacitance is increased to dampen switching oscillations, then the amplitude of drain voltage oscillations is reduced, but the device complexity increases
Solution Approach 1:
The gate connection terminal is extended from the conventional planar configuration into the edge region of the semiconductor body, utilizing the third dimension (depth/vertical extension) to achieve additional capacitive coupling. This dimensional transition allows the gate terminal to overlap with the edge termination region, thereby increasing the gate-drain capacitance without requiring additional external components.
Solution Approach 2:
The gate connection terminal is nested within the edge region structure, where it partially superimposes on the edge termination region. This nesting arrangement allows the gate terminal to be integrated within the existing device geometry, utilizing the space between the active area and the outer perimeter to establish additional capacitive coupling paths.
2Reliability
If the gate resistance is increased to reduce switching oscillations, then the oscillation amplitude is reduced, but the switching speed decreases
Solution Approach 1:
Instead of changing the gate resistance parameter, the invention changes the capacitive coupling parameter by extending the gate terminal into the edge region. This parameter substitution approach allows oscillation damping to be achieved through capacitance modification rather than resistance modification, thereby avoiding the trade-off between oscillation reduction and switching speed.
3Area of stationary object
If the gate terminal extension is reduced to form body wells closer together, then the device area is reduced, but the gate-drain capacitance decreases and oscillation amplitude increases
Solution Approach 1:
The invention compensates for reduced gate terminal extension by utilizing the vertical dimension - extending the gate connection terminal downward into the edge region to overlap with the edge termination region. This vertical extension creates additional capacitive coupling area that compensates for the reduced horizontal gate terminal extension, maintaining adequate gate-drain capacitance despite compact device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased feedback capacitance effectively dampens the amplitude of drain voltage oscillations during the turn-OFF step, reducing power losses and mitigating electromagnetic interference, thus enhancing the reliability and efficiency of SiC MOSFETs in power electronics.
Implementation Method 1
a gate connection terminal of conductive material, electrically coupled to the gate region, extending on the front side partially superimposed on the edge termination region and capacitively coupled with a portion of the semiconductor body adjacent and external to the edge termination region
Data Source
AI summary
The present disclosure is directed to an electronic device including a semiconductor body having a first electrical conductivity and provided with a front side; an active area of the semiconductor body, accommodating the source and gate regions of the electronic device and configured to accommodate, in use, a conductive channel of the electronic device; and an edge region of the electronic device, surrounding the active area. The edge region accommodates at least in part: i) an edge termination region, having a second electrical conductivity opposite to the first electrical conductivity, extending into the semiconductor body at the front side; and ii) a gate connection terminal of conductive material, electrically coupled to the gate region, extending on the front side partially superimposed on the edge termination region and capacitively coupled with a portion of the semiconductor body adjacent and external to the edge termination region.