SiC MOSFET P+ Region Optimization for Parasitic Suppression
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Solution Overview
Problem
Traditional silicon carbide MOSFET device manufacturing processes face challenges in forming a self-aligned P+ region, leading to parasitic transistor effects and breakdown issues due to shallow implantation and high energy requirements, which affect device performance and increase production costs.
Innovation Solution
A self-aligned silicon carbide MOSFET device with a P+ region optimized through heavy doping of Al and B ions, where the P+1 region is formed with high doping concentration and the P+2 region is diffused to the bottom of the P well, using a novel manufacturing method that includes ion implantation and high-temperature activation annealing to control channel size and prevent parasitic transistor effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the P+ region is shallowly implanted to form good source ohmic contact and short-circuit connection, then contact resistance is reduced, but parasitic transistor effects (NPN and PiN) occur leading to breakdown
Solution Approach 1:
The patent applies local quality by creating distinct doping regions with different characteristics: the P+ contact region is heavily doped (1E19-1E20 cm^-3) for low contact resistance, while the P+ channel stop region has moderate doping (1E17-1E18 cm^-3) to prevent parasitic effects. This spatial differentiation of doping concentrations resolves the contradiction between good contact quality and parasitic transistor prevention.
2Reliability
If the P+ region is deeply and heavily doped to prevent parasitic transistor effects, then device reliability is improved, but implantation time and cost increase significantly
Solution Approach 1:
The patent segments the P+ doping into two separate implantation processes: first forming the P+ contact region with heavy doping at lower energy (30-50 keV, 1E15-1E16 cm^-2), then forming the P+ channel stop region with moderate doping at higher energy (100-200 keV, 1E14-1E15 cm^-2). This segmentation avoids the need for single high-energy-high-dose implantation, reducing both time and cost while achieving reliable parasitic prevention.
3Object-affected harmful factors
If high energy and high dose ion implantation is used to achieve deep P+ doping, then parasitic transistor effects are suppressed, but activation annealing quality deteriorates
Solution Approach 1:
The patent uses partial action by implementing moderate doping (1E17-1E18 cm^-3) in the P+ channel stop region rather than extreme heavy doping. This moderate level is sufficient to prevent parasitic PiN depletion and stabilize the channel, while avoiding the excessive damage that would degrade activation annealing quality. The two-stage implantation process enables this controlled partial action.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized P+ region reduces on-resistance, prevents parasitic transistor activation, and simplifies the manufacturing process, enabling the production of high-voltage, high-frequency silicon carbide MOSFET devices with improved conduction and breakdown characteristics.
Implementation Method 1
both the P+1 region and the P+2 region are formed with heavy doping in an ion implantation way
Implementation Method 2
a method for manufacturing the same, comprising: step 1 of cleaning a SiC wafer; step 2 of forming a P well
Implementation Method 3
the P+2 diffusion region is formed in a diffusion way, which is diffused till a bottom of the P well or even lower than the bottom of the P well
Data Source
AI summary
The present disclosure discloses a self-aligned silicon carbide MOSFET device with an optimized P+ region and a manufacturing method thereof. The self-aligned silicon carbide MOSFET device is formed by a plurality of silicon carbide MOSFET device cells connected in parallel, and these silicon carbide MOSFET device cells are arranged evenly. The silicon carbide MOSFET device cell comprises two source electrodes, one gate electrode, one gate oxide layer, two N+ source regions, two P+ contact regions, two P wells, one N− drift layer, one buffer layer, one N+ substrate, one drain electrode and one isolation dielectric layer. By optimizing the P+ region, the present disclosure forms a good source ohmic contact, reduces the on-resistance, and also shorts the source electrode and the P well to prevent the parasitic transistor effect of the parasitic NPN and PiN, which may take both conduction characteristics and the breakdown characteristics of the device into consideration, and may be applied to a high voltage, high frequency silicon carbide MOSFET device. The self-aligned manufacturing method used in the present disclosure simplifies the process, controls a size of a channel accurately, and may produce a lateral and vertical power MOSFET.