SiC MOSFET Fan-Out Package Layout for Pad Separation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in maximizing the size of source pads and achieving minimum separation between source and gate pads, leading to issues such as elevated risk of STM peeling and reduced performance due to design rule constraints.
Innovation Solution
A fan-out package design is implemented, where the gate pad extends beyond the perimeter of the semiconductor die, allowing for a larger source pad size and minimizing the risk of STM peeling by applying Ag sinter material only to the redistribution layer, eliminating the need for direct application on the gate contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate pad is kept within the die perimeter, then the source pad size can be maximized, but the separation between source and gate pads cannot meet design rules
Solution Approach 1:
The gate pad is extended in the lateral dimension beyond the die perimeter, utilizing the plane area outside the die to achieve the required separation distance from the source pad. This dimensional extension allows both the source pad to maintain large area and the gate pad to be sufficiently separated, resolving the contradiction between maximizing source pad size and maintaining proper pad separation.
Solution Approach 2:
The gate pad structure is segmented into two parts: a portion within the die perimeter and an extended portion outside the die perimeter. This segmentation allows the gate pad to fulfill its electrical function within the die while extending outward to achieve the required separation distance, thereby preventing STM peeling without compromising source pad size.
2Reliability
If the gate pad is extended beyond the die perimeter, then separation from source pad is achieved, but the package complexity increases
Solution Approach 1:
The extended gate pad structure serves multiple functions: it provides the required separation distance from the source pad to prevent STM peeling, maintains electrical connectivity through the redistribution layer, and utilizes the existing die perimeter as a natural boundary. This multi-functionality reduces the need for additional complex structures to achieve pad separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design maximizes source pad size, reduces resistance, and minimizes hot spots, while adhering to design rules by ensuring a minimum separation between source and gate pads, enhancing overall package performance.
Implementation Method 1
pressure sintering one or more gate pads and one or more source pads of one or more semiconductor die with the Ag sinter material
Data Source
AI summary
A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.