SiC MOSFET Pillar Structure for Electric Field Distribution
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Solution Overview
Problem
Silicon carbide MOSFETs with trench gates face premature breakdown due to electric field concentration, resulting in lower breakdown voltage and higher on-resistance compared to conventional silicon MOSFETs.
Innovation Solution
The semiconductor device design includes n+ and p type pillar regions within an n− epitaxial layer, spaced apart from a trench, which distributes the electric field through a PN junction, improving breakdown voltage and reducing on-resistance by providing an alternative current path to the drain electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a trench gate structure is used in silicon carbide MOSFET, then the device can achieve high current capacity and fast switching characteristics, but electric field concentration at the trench bottom causes premature breakdown and reduces breakdown voltage
Solution Approach 1:
The device is divided into multiple independent pillars (n-type and p-type) that are spaced apart from the trench. Each pillar acts as an independent current path and electric field management unit, preventing concentration at the trench bottom while maintaining high current capacity through parallel conduction paths
Solution Approach 2:
The n-type and p-type pillars serve as intermediary structures between the trench gate and the substrate. These pillars mediate the electric field distribution by providing alternative paths that prevent direct field concentration at the trench bottom, thereby improving breakdown voltage while maintaining the trench gate's high current capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances breakdown voltage and reduces on-resistance in silicon carbide MOSFETs by spreading the electric field and offering a direct path for electron current, outperforming conventional trench MOSFETs in current-voltage characteristics.
Implementation Method 1
an n− type epitaxial layer, a plurality of n type pillar regions, and a plurality of p type pillar regions disposed on a first surface of the n+ type silicon carbide substrate... a first p type pillar region of the plurality of p type pillar regions is disposed within the n− type epitaxial layer
Implementation Method 2
forming a plurality of n type pillar regions by first epitaxial growth on the first portion of the first surface of the n+ type silicon carbide substrate
Data Source
AI summary
A semiconductor device includes an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region sequentially disposed on the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate.