SiC Power MOSFET Radiation Hardening via Buffer Layer
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Solution Overview
Problem
Current semiconductor devices, particularly power MOSFETs, face challenges in achieving high breakdown voltage and low RDSON while maintaining reliability in harsh environments, such as aerospace, due to defects in SiC substrates and radiation exposure, which increases manufacturing costs and defect density.
Innovation Solution
A method is developed to form a substantially defect-free SiC substrate using sacrificial heteroepitaxy and micro-pillar structures to relieve stress, followed by direct wafer bonding and deep reactive ion etching to create high-breakdown voltage trench gate power MOSFETs with embedded SiC, enhancing radiation hardness and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If SiC layer is formed on Si substrate, then breakdown voltage and heat dissipation are improved, but defect density increases due to heterointerface stress
Solution Approach 1:
A buffer layer is introduced between the SiC layer and Si substrate to act as an intermediary that reduces stress at the heterointerface. This buffer layer absorbs thermal expansion differences and prevents defect propagation, enabling high-quality SiC growth while maintaining the beneficial electrical properties of the SiC-Si heterostructure.
Solution Approach 2:
The device structure is segmented into distinct functional layers: Si substrate, buffer layer, and SiC active layer. This segmentation allows each layer to be optimized independently - the Si substrate provides mechanical support and cost benefits, the buffer layer manages stress, and the SiC layer delivers high breakdown voltage and power handling capability.
2Productivity
If conventional SiC substrate manufacturing is used, then production capacity is maintained, but defect density remains high and yield is low
Solution Approach 1:
The buffer layer serves as a mediator that enables high-yield SiC production by preventing defect formation during epitaxial growth. This allows manufacturers to maintain high production capacity using conventional CMOS-compatible processes while achieving dramatically improved yield through the stress-managing buffer layer.
3Object-affected harmful factors
If radiation hardening is implemented through traditional methods, then radiation resistance is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The buffer layer composition and thickness are carefully controlled to create a structure that inherently resists radiation damage. By adjusting the buffer layer parameters during standard epitaxial growth, radiation hardening is achieved without adding complex processing steps or increasing device structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in power MOSFETs with improved breakdown voltage, reduced RDSON, and increased radiation hardness, suitable for demanding applications like aerospace, while lowering manufacturing costs by confining defects to sacrificial layers and removing them, thus achieving high-performance and reliability.
Implementation Method 1
forming a substantially defect-free SiC substrate using sacrificial heteroepitaxy
Implementation Method 2
deep reactive ion etching to create high-breakdown voltage trench gate power MOSFETs
Implementation Method 3
direct wafer bonding to create high-breakdown voltage trench gate power MOSFETs
Data Source
AI summary
A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third semiconductor layer made of the second semiconductor material can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device or electrical component is formed in the second semiconductor layer. The electrical component can be a power MOSFET. A first insulating layer, such as an oxide layer, is formed over the electrical component, and second insulating layer, such as a nitride layer, is formed over the first insulating layer for protection against radiation.