Ring-Shaped SiC MOSFET Channels for Lower Oxide Field Stress
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Solution Overview
Problem
Conventional power MOSFETs face a tradeoff between on-state resistance and reliability due to gate oxide layer breakdown under high electric fields, which is exacerbated by reducing doping concentrations to lower electric fields, leading to increased on-state resistance and reduced switching speeds.
Innovation Solution
Incorporating ring-shaped channel regions and strategically designed gate electrodes with openings to increase channel area without increasing device size, thereby reducing electric fields and improving reliability while maintaining low on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doping concentration is reduced to lower electric fields, then reliability is improved, but on-state resistance increases
Solution Approach 1:
The patent transitions from conventional linear channel regions to ring-shaped channel regions, adding a radial dimension to current flow. This geometric transformation increases the effective channel area without proportionally increasing the footprint, allowing more current paths while maintaining compact device structure and reducing on-state resistance despite lower doping concentrations
Solution Approach 2:
The ring-shaped channel region is divided into multiple segments around the JFET region, creating distributed current paths. This segmentation increases the total channel area and provides multiple parallel conduction paths, reducing the overall on-state resistance while maintaining lower doping concentrations for improved reliability
2Object-affected harmful factors
If device size is increased to increase channel area, then on-state resistance decreases, but device complexity increases
Solution Approach 1:
The ring-shaped channel configuration utilizes radial symmetry to increase channel area within a compact circular footprint. This geometric approach increases the effective channel area by factor compared to linear channels of equivalent footprint, reducing on-state resistance without proportionally increasing device size or complexity
Solution Approach 2:
The gate electrode structure is merged with openings positioned over the JFET regions, creating an integrated structure that serves multiple functions: defining the channel region, providing electrical connection, and reducing electric field concentration. This merging reduces the number of separate components and simplifies the overall device structure
3Reliability
If gate oxide layer thickness is increased to reduce electric field, then reliability is improved, but switching speed decreases
Solution Approach 1:
The patent changes the geometric parameters of the channel region from linear to ring-shaped, increasing the channel area and reducing current density. This parameter change allows the use of thinner gate oxide layers because the reduced electric field intensity (due to distributed current paths) lowers the stress on the gate oxide, maintaining reliability while enabling faster switching with thinner dielectric layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and performance of power MOSFETs by reducing electric fields in the gate oxide layers, improving on-state resistance, and extending the device's lifespan under short circuit conditions.
Implementation Method 1
An n-type MOSFET turns on when a gate bias voltage is applied to the gate electrode that is sufficient to create a conductive n-type inversion layer in the p-type channel region, thereby electrically connecting the n-type source and drain regions
Implementation Method 2
The gate forms a capacitor with the channel region. Thus, only minimal charging and discharging current is required during switching
Data Source
AI summary
A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that includes a drift region having a first conductivity type, a plurality of channel regions that each have a second conductivity type, and a plurality of JFET regions that each have the first conductivity type. Each channel region comprises a ring-shaped channel region that has a ring shape and surrounds a respective one of the JFET regions when viewed in plan view.