SiC MOSFET Cell Structure for Short-Circuit Tolerance and Low Diode Drop
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Solution Overview
Problem
Silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) face issues with high short-circuit current density, low short-circuit tolerance, short short-circuit time, and high forward voltage drop of a body diode, limiting their performance in applications like electric vehicles and renewable energy systems.
Innovation Solution
The design incorporates alternating cells with specific well regions, source regions, and contact layers, including ohmic and Schottky contacts, to reduce channel density, enhance short-circuit tolerance, and minimize reverse leakage current and forward voltage drop, while maintaining the transistor's size and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional SiC MOSFET structure is used, then high power density and high operating frequency are achieved, but high short-circuit current density and low short-circuit tolerance occur
Solution Approach 1:
The source region is divided into multiple discrete source regions instead of a continuous source region. This segmentation reduces the total channel width and consequently reduces the short-circuit current density while maintaining the power handling capability through optimized cell layout and parallel conduction paths.
Solution Approach 2:
Different regions of the device are assigned different doping concentrations and geometries to optimize local performance. The source regions have specific doping levels and dimensions that differ from the drift region, allowing localized control of current density and electric field distribution to improve short-circuit tolerance without compromising overall power density.
2Device complexity
If conventional body diode structure is used, then simple device structure is maintained, but high forward voltage drop occurs
Solution Approach 1:
The body diode function is merged with the MOSFET structure by utilizing the intrinsic diode formed between the drain and source regions. The discrete source regions create inherent pn junctions that function as body diodes, eliminating the need for separate diode structures and reducing forward voltage drop through optimized junction geometry and doping profiles.
3Reliability
If discrete source regions are introduced, then short-circuit current density is reduced, but device structure becomes more complex
Solution Approach 1:
The discrete source regions serve multiple functions simultaneously: they define the channel boundaries for MOSFET operation, create the pn junctions for body diode functionality, and control the short-circuit current density. This multi-functionality reduces the need for additional structures and minimizes overall device complexity while achieving improved short-circuit tolerance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces short-circuit current density, improves short-circuit tolerance, prolongs short-circuit time, and decreases the reverse leakage current of the Schottky diode, while lowering the forward voltage drop, resulting in a more reliable and efficient SiC MOSFET with improved performance characteristics.
Implementation Method 1
a fourth settling part in Schottky contact with the third deep well region, the fourth deep well region and the epitaxial layer
Data Source
AI summary
Some embodiments of the present disclosure provide a silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method. The transistor includes first and second cells which jointly include a drain electrode layer, an ohmic contact layer, a substrate layer, an epitaxial layer, an interlayer dielectric layer, and a source electrode layer, the first cell further includes a first deep well region, a second deep well region, a first shallow well region, a second shallow well region, a two first source region, a two second source region, a first gate oxide layer, and a first polysilicon gate, and the second cell further includes a third deep well region, a fourth deep well region, a third shallow well region, a fourth shallow well region, a second gate oxide layer, a third gate oxide layer, a second polysilicon gate, and a third polysilicon gate.