SiC Power MOSFET Safe Operating Area via Segmented Cells
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Solution Overview
Problem
Silicon-carbide (SiC) vertical power MOSFET devices face thermal instability and limited Safe Operating Area (SOA) due to non-uniform temperature distribution and negative temperature coefficient of the threshold voltage, which restricts their high voltage and high current operations, making them unsuitable for applications requiring linear operation and high frequency usage.
Innovation Solution
The implementation of terraced oxide and notched poly gate structures, combined with strategic placement of active and inactive cells, and in-situ ballast resistors, aims to create a uniform temperature distribution and a negative temperature coefficient of the channel mobility, thereby enhancing the SOA of SiC power MOSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the density of cells is increased to reduce On Resistance, then the cell structure becomes more compact and Rdson decreases, but thermal instability is aggravated due to high packing density and non-uniform temperature distribution
Solution Approach 1:
The device is divided into multiple independent cells with individual source contacts. By segmenting the device into discrete cells rather than a continuous structure, the patent enables independent thermal management of each cell, preventing thermal runaway from propagating across the entire device while maintaining high current density capability
Solution Approach 2:
Different regions of the device are given different properties: the drift region has specific doping concentrations optimized for high voltage blocking, while the JFET regions have tailored doping profiles to control channel formation. This local differentiation allows optimization of each region's function while managing thermal characteristics
2Power
If the device is operated at high voltage and high current to increase power capability, then the power rating increases, but thermal runaway is triggered due to negative temperature coefficient of threshold voltage
Solution Approach 1:
The patent implements inherent negative feedback through the device structure: as temperature increases in a cell, the threshold voltage decreases, which would normally increase current, but the localized source contact and cell segmentation create a feedback mechanism that limits current concentration and prevents thermal runaway by distributing stress across multiple cells
Solution Approach 2:
The device structure is designed with built-in protective features before operation: the drift region doping profile and JFET region geometry are configured to create a safety margin that prevents thermal instability from developing into thermal runaway, cushioning against the harmful effects of negative temperature coefficient
3Quantity of substance
If the die size is increased to accommodate higher current ratings, then the current capability increases, but the non-uniform temperature distribution is aggravated leading to thermal instability
Solution Approach 1:
The large die is segmented into multiple smaller cells, each with its own source contact and drain region. This segmentation creates multiple independent thermal zones that can be managed separately, preventing non-uniform temperature distribution from causing thermal instability even in large area devices
Solution Approach 2:
The patent transitions from a planar two-dimensional cell layout to a three-dimensional structure with vertically stacked source and drain regions. This vertical dimension allows for improved heat dissipation pathways and more uniform temperature distribution across the die area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the SOA of SiC power MOSFETs by ensuring thermal stability and reducing the risk of thermal runaway, making them suitable for high voltage and high current applications, including those requiring linear operation and high frequency usage.
Implementation Method 1
The implementation of terraced oxide and notched poly gate structures, combined with strategic placement of active and inactive cells, and in-situ ballast resistors, aims to create a uniform temperature distribution
Implementation Method 2
in-situ ballast resistors, aims to create a uniform temperature distribution
Data Source
AI summary
A SiC Power Semiconductor device of the Field Effect Type (MOSFET, IGBT or the like) with “muted” channel conduction, negative temperature coefficient of channel mobility, in situ “ballasted” source resistors and optimized thermal management of the cells for increased Safe Operating Area is described. Controlling the location of the Zero Temperature Crossover Point (ZTCP) in relationship to the drain current is achieved by the partition between the “active” and “inactive” channels and by adjusting the mobility of the carriers in the channel for the temperature range of interest. The “Thermal management” is realized by surrounding the “active” cells/fingers with “inactive” ones and the “negative” feedback of the drain/collector current due to local increase of the gate bias is achieved by implementing in-situ “ballast” resistors inside of each source contact.