SiC MOSFET Cell Geometry With Segmented JFET Width for Lower On-Resistance

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Solution Overview

Problem

Conventional silicon carbide (SiC) MOSFETs face challenges in minimizing on-state resistance while maintaining off-state breakdown voltage, due to limitations in cell geometry and fabrication techniques, leading to increased resistance and reliability issues.

Innovation Solution

The semiconductor device cell design increases the relative proportion of the JFET region between adjacent cells, maintaining the geometry of the channel region at cell corners, which reduces on-state resistance without degrading off-state breakdown voltage, by optimizing the JFET region width and arrangement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the JFET region width is increased to reduce on-state resistance, then the on-state resistance decreases, but the off-state breakdown voltage may be degraded

Engineering Contradiction:

Improveon-state resistanceVSAvoidoff-state breakdown voltage

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the JFET region width at different locations within the cell. The intermediate region between channel regions has a greater width than the JFET region at cell corners. This local variation allows the intermediate region to contribute more to reducing on-state resistance while the corner regions maintain geometry that preserves off-state breakdown voltage characteristics.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The JFET region is segmented into distinct zones with different width characteristics: a first JFET region at cell corners with one width geometry, and a second JFET region (intermediate region) between channel regions with a greater width. This segmentation allows independent optimization of each zone's contribution to overall device performance.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If conventional cell geometry is used, then fabrication is simpler, but on-state resistance is higher and reliability is reduced

Engineering Contradiction:

Improvefabrication simplicityVSAvoiddevice performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the geometric parameters of the JFET region by defining different width measurements at different locations. The first width (at corners) and second width (intermediate region) are distinct parameters that can be independently optimized. This parameter differentiation improves device performance while remaining compatible with conventional fabrication processes.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentEP4415052A1Semiconductor switching device

Publication Date: 2024.08.14 GE AVIATION SYSTEMS LLC

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AI summary

A semiconductor device cell (150) includes a JFET region (29) adjacent a channel region (28) and defines a periphery of the semiconductor device cell (150). The JFET region (29) includes a JFET segment (29c) having a first end (29a) disposed proximal a first corner (69a) of the semiconductor device cell (150) and an opposing second end (29b) proximal a second corner (69b) of the semiconductor device cell (150). The JFET segment (29c) has a first width (W1) between the first end (29a) and the second end (29b) that is greater than a second width (W2) of the JFET region (29) the first end (29a) and the second end (29b).