SiC MOSFET Gate Pad Insulation Reliability via Segmented Source Wiring
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Solution Overview
Problem
SiC MOSFETs face high risk of interlayer insulating film deterioration due to high dV/dt during fast switching, which increases the potential below the gate wiring or gate pad, and conventional structures with source wiring around the gate wiring result in a low effective area to chip area ratio, increasing costs.
Innovation Solution
A semiconductor device design featuring a substrate with a drift layer and high impurity concentration region under the gate wiring and gate pad, where the source wiring and gate wiring form a frame around the source electrode, increasing the effective area to chip area ratio and reducing voltage under the gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source wiring is provided around the gate wiring to reduce potential below the gate, then the risk of interlayer insulating film deterioration is reduced, but the effective area to chip area ratio decreases
Solution Approach 1:
The source wiring is divided into two parts: source wiring opposed to the source electrode (providing current carrying function) and source wiring opposed to the gate pad (reducing potential below gate). This segmentation allows each part to optimize its function without compromising the other, resolving the contradiction between reliability and effective area ratio
Solution Approach 2:
Different regions of the source wiring are assigned different functions based on local requirements. The source wiring opposed to the source electrode maximizes current carrying capability, while the source wiring opposed to the gate pad specifically addresses potential reduction below the gate structure, achieving local optimization that resolves the overall contradiction
2Reliability
If source wiring surrounds the gate wiring to reduce potential below the gate, then the risk of interlayer insulating film deterioration is reduced, but the chip size increases for the same effective area
Solution Approach 1:
The source wiring is segmented into functional zones: one zone opposed to the source electrode for current carrying and another zone opposed to the gate pad for potential control. This segmentation eliminates the need for a complete surrounding structure, reducing chip size while maintaining reliability
Solution Approach 2:
The patent extracts only the necessary portions of source wiring that are opposed to the gate pad for potential control, rather than requiring a complete surrounding structure. This extraction reduces the overall chip size while still achieving the reliability goal of reducing potential below the gate
Data Source
AI summary
In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.