SiC Power MOSFET With Selectively Grown Pillars
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Solution Overview
Problem
Power semiconductor devices, particularly low voltage class power SiC MOSFETs, face challenges with low inversion channel mobility leading to poor on-resistance, which affects switching and conduction losses, especially in applications like electric and hybrid electric vehicles.
Innovation Solution
The development of a power semiconductor device with a semiconductor layer stack comprising selectively grown SiC pillars of n-type SiC, utilizing a 'gate-first' integration process and a superjunction structure with a thin insulator layer, enhancing channel mobility and reducing defects, thereby improving switching and conduction losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power semiconductor devices use inversion channel structure, then device structure is simple, but channel mobility is low leading to poor on-resistance
Solution Approach 1:
The patent inverts the conventional approach by using an accumulation channel structure instead of an inversion channel structure. The accumulation channel is formed by a highly doped n-type semiconductor layer (first doping concentration) beneath the gate insulator, which accumulates majority carriers (electrons) to form a high-mobility conduction path, thereby improving on-resistance while maintaining structural feasibility
Solution Approach 2:
The patent applies local quality by creating a specialized accumulation channel region with distinct doping characteristics (high n-type doping concentration of at least 1×10^19 atoms/cm³) localized beneath the gate insulator, while the rest of the drift region maintains lower doping concentration. This localized high-doping region provides high carrier mobility exactly where needed for conduction, resolving the contradiction between simple structure and low on-resistance
2Reliability
If selectively grown SiC pillars are used with accumulation channel, then channel carrier mobility is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the gate insulator and gate electrode structure before growing the semiconductor pillars. The gate insulator is deposited on a planarized surface, and the gate electrode is formed subsequently. Only after this gate structure is in place are the n-type SiC pillars selectively grown through the gate electrode, ensuring the accumulation channel forms with correct doping concentration and positioning relative to the gate structure
Solution Approach 2:
The patent utilizes self-service through self-aligned growth where the semiconductor pillars grow selectively through openings in the gate electrode structure without requiring additional alignment steps. The selective epitaxial growth automatically positions the pillars and forms the accumulation channel in the correct location beneath the gate insulator, reducing manufacturing complexity despite the advanced structure
3Loss of energy
If high doping concentration is used in accumulation channel, then switching losses are reduced, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by precisely controlling the doping concentration parameter in the accumulation channel to be at least 1×10^19 atoms/cm³, which is significantly higher than the drift region doping concentration (1×10^15 to 1×10^18 atoms/cm³). This parameter change in doping concentration creates high carrier density and mobility in the accumulation channel, reducing switching losses while the doping profile is managed through selective epitaxial growth conditions rather than complex additional structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high channel carrier mobility, enabling efficient power semiconductor devices with improved switching and conduction performance, suitable for high-power applications in vehicles and other demanding electrical systems.
Implementation Method 1
oxidizing the semiconductor mask, wherein tubes of an insulator material are formed around pillars
Implementation Method 2
selectively grown SiC pillars in a semiconductor layer stack
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
In at least one embodiment, the power semiconductor device (1) comprises - a first main electrode (21), - a second main electrode (22), - a semiconductor layer stack (3) and a gate electrode layer (4) between the electrodes (21, 22), wherein - the semiconductor layer stack (3) comprises a plurality of pillars (30) traversing the gate electrode layer (4), - the whole semiconductor layer stack (3) is of the same conductivity type, - each one of the pillars (30) comprises a top region (31) with a first doping concentration, - at sides of the top regions (31) facing away from the first main electrode (21), each of the pillars (30) comprises a channel region (32) with a second doping concentration, and - the first doping concentration exceeds the second doping concentration by at least a factor of 10.