SiC MOSFET Self-Aligned Gate and Source Contacts
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Solution Overview
Problem
The challenge in fabricating silicon carbide (SiC) based metal oxide field effect transistors (MOSFETs is to reduce the spacing between gate and source contacts to enhance packing density and switching performance while maintaining manufacturable yield, as existing methods often result in contact shorting due to poor alignment.
Innovation Solution
A method involving the formation of a source region and gate oxide layer on a SiC layer, followed by depositing a gate electrode and conductive layer, and subjecting them to high temperatures to form metal silicide contacts with a spacing of less than 0.6 μm between the gate and source contacts, using self-aligned techniques to ensure accurate alignment and prevent shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between gate and source contacts is reduced to increase cell packing density, then the on-resistance and switching performance are enhanced, but the manufacturable yield decreases due to contact shorting from poor alignment
Solution Approach 1:
The gate contact is formed first, and then the source contact is formed in a subsequent self-aligned process. This preliminary formation of the gate contact structure allows the source contact to be automatically positioned relative to it, ensuring proper alignment even at reduced spacings of less than 0.6 μm, thereby preventing contact shorting while maintaining high cell packing density
Solution Approach 2:
The self-aligned fabrication method uses the previously formed gate contact structure as a reference for positioning the source contact. The process automatically ensures correct spacing and alignment without requiring additional complex alignment steps, enabling reliable manufacturing of closely packed cells while maintaining high yield
2Area of stationary object
If the spacing between gate and source contacts is reduced, then the device area is decreased and packing density is increased, but the alignment precision required increases making manufacturing more difficult
Solution Approach 1:
The gate contact structure is formed in advance before the source contact. This preliminary structure serves as a physical reference that automatically defines the positioning of the source contact, eliminating the need for high-precision external alignment and enabling reduced device area while maintaining manufacturability
Solution Approach 2:
The fabrication process uses the gate contact itself as the alignment reference for forming the source contact. This self-aligned approach automatically ensures the required spacing and orientation, reducing the device area to less than 0.6 μm spacing without compromising alignment precision or increasing manufacturing difficulty
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased packing density and improved switching performance of SiC MOSFETs by reducing contact resistance and preventing shorting, thereby enhancing the manufacturable yield and operational efficiency of the devices.
Implementation Method 1
forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide
Implementation Method 2
forming a source region on a SiC layer and annealing the source region
Data Source
AI summary
The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.