SiC MOSFET Self-Aligned Layout for Smaller Cell Pitch
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Solution Overview
Problem
Conventional fabrication methods for silicon carbide MOSFETs face challenges in reducing cell size and mask layers, leading to increased manufacturing complexity and cost due to misalignment issues and the need for multiple masks.
Innovation Solution
A fabrication method that reduces the number of masks by using self-aligning processes for forming P-plus and N-plus layers, employing spacers and dimple etching to define poly gates and contacts, and utilizing different dielectric materials for interlayer dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask layers are used to define different regions in the conventional fabrication process, then the different regions can be formed with proper alignment, but the cell pitch cannot be reduced and the manufacturing complexity and cost increase
Solution Approach 1:
The patent employs self-aligning processes where previously formed structures (such as P-well regions, spacers, and dimple patterns) automatically serve as alignment references for subsequent steps. The spacers are formed conformally on the sidewalls of existing structures, ensuring precise positioning without requiring additional mask alignment. This self-service mechanism eliminates the need for multiple masks while maintaining manufacturing precision.
Solution Approach 2:
The patent performs preliminary actions by forming spacers and dimple patterns in advance that will serve as alignment guides for later steps. The P-well mask is formed first, followed by spacer deposition that automatically positions subsequent implantation regions. This preliminary structuring creates a self-aligning framework that simplifies all subsequent fabrication steps without compromising precision.
2Device complexity
If the number of mask layers is reduced to simplify the fabrication process, then manufacturing complexity and cost are reduced, but misalignment issues may occur
Solution Approach 1:
The patent replaces mask-based alignment with self-aligning mechanisms where the device structures themselves provide the alignment reference. Spacers are deposited conformally on sidewalls of previously formed structures, automatically ensuring precise positioning. The dimple etching process uses the spacer patterns as self-generated masks, eliminating the need for external mask layers while maintaining alignment precision through the self-service nature of the process.
Solution Approach 2:
The patent introduces spacers as intermediary structures that mediate between different fabrication steps. These spacers serve as both structural elements and alignment references, acting as intermediaries that connect the P-well formation step with subsequent N-plus and P-plus implantation steps. The spacers physically bridge the gap between different regions, ensuring precise alignment without requiring mask layers.
3Length of moving object
If dimple etching and self-aligning processes are used to reduce cell size, then smaller cell pitch is achieved, but the fabrication process becomes more complex
Solution Approach 1:
The patent segments the fabrication process into distinct modular steps: P-well formation, spacer deposition, N-plus implantation through spacers, P-plus implantation, and dimple etching. Each segment is self-contained and builds upon the previous one, allowing for systematic reduction of cell pitch. The segmentation of functions into separate process modules enables precise control of each step while maintaining overall process simplicity through the self-aligning nature of the sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables smaller cell pitch and lower specific on-resistance, simplifies the fabrication process, reduces manufacturing costs, and improves manufacturing tolerance while maintaining electrical performance.
Implementation Method 1
implanting the semiconductor substrate through the P-well mask to form a P-well region; implanting the P-well region through the spacer to form an N-plus layer; implanting the semiconductor substrate through the P-plus mask to form a P-plus layer
Implementation Method 2
disposing a gate oxide layer on the semiconductor substrate by an oxidation process
Data Source
AI summary
A fabrication method of forming a silicon carbide MOSFET is provided. The fabrication method includes the step of providing a semiconductor substrate. A P-well region is formed by implanting the semiconductor substrate through the P-well mask. A spacer is disposed on sidewall of the P-well mask and the P-well region is implanted to form an N-plus layer. A P-plus mask is disposed on the semiconductor substrate and the semiconductor substrate is implanted to form a P-plus layer. A gate oxide layer, a poly gate and a first interlayer dielectric layer are formed on the semiconductor substrate. A second interlayer dielectric layer is disposed on sidewall of the poly gate and the first interlayer dielectric layer. A metal layer is disposed to cover the first interlayer dielectric layer and the second interlayer dielectric layer.