SiC MOSFET Current Sensor Gate Runner ESD Protection
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Solution Overview
Problem
Conventional semiconductor devices with silicon carbide (SiC) MOSFETs have a current sensor with low electrostatic discharge (ESD) tolerance due to a smaller surface area and lower gate capacitance compared to the main semiconductor device, making them prone to breakdown.
Innovation Solution
A semiconductor device design with a wider bandgap material, such as SiC, featuring a second gate runner that increases the gate capacitance of the current sensor, reducing transient voltages and enhancing ESD tolerance by connecting it to the main gate runner and including an internal resistor or inductor to manage gate current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the current sensor is designed with a smaller surface area to reduce device complexity, then the device complexity is reduced, but the gate capacitance decreases making the current sensor more susceptible to ESD damage
Solution Approach 1:
A second gate runner is introduced as an intermediary component between the gate pad and the gate electrode of the current sensor. This second gate runner has a larger surface area than the first gate runner, thereby increasing the gate capacitance of the current sensor and improving its ESD tolerance without requiring the current sensor itself to have a larger surface area.
2Reliability
If the gate capacitance of the current sensor is increased to improve ESD tolerance, then the ESD tolerance is improved, but the device complexity and surface area requirements increase
Solution Approach 1:
The second gate runner serves multiple functions: it acts as a connection path for gate signals, provides additional gate capacitance for ESD protection, and can be configured to extend along boundary regions to optimize both electrical performance and physical layout efficiency.
3Reliability
If the second gate runner extends along the boundary between the first device region and the edge termination region, then the gate capacitance is increased, but the device layout complexity increases
Solution Approach 1:
The second gate runner is configured to extend in a spatial dimension along the boundary region between the first device region and the edge termination region. This dimensional arrangement allows the gate runner to achieve sufficient length and surface area for increased gate capacitance while utilizing the available layout space efficiently along the device periphery.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the ESD tolerance and reduces transient voltages of the current sensor by increasing its gate capacitance and managing gate current, ensuring more stable operation.
Implementation Method 1
A semiconductor device design with a wider bandgap material, such as SiC, featuring a second gate runner that increases the gate capacitance of the current sensor, reducing transient voltages and enhancing ESD tolerance
Data Source
AI summary
In an edge termination region, a second gate runner for a current sensor is formed between a first gate runner for a main semiconductor device and an active region. The second gate runner surrounds the periphery of the active region in a substantially rectangular shape having an opening. One end of the second gate runner is connected to all of the gate electrodes of the current sensor, and the other end is connected to the first gate runner at between a gate pad and an OC pad. This makes it possible to increase the gate capacitance of the current sensor as the current sensor switches ON and OFF when a pulse-shaped gate voltage is applied to the gate pad by an amount proportional to the surface area of the second gate runner.