SiC Power MOSFET Shield Region for Gate Oxide Field Protection
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Solution Overview
Problem
MOSFET transistors, especially power MOSFETs made from silicon carbide, face the issue of elevated electric fields at the gate oxide, which can lead to deterioration or destruction of the oxide layer, rendering the transistor useless.
Innovation Solution
A semiconductor device is designed with a shielding region located below the JFET region, between the well regions, and connected to the source terminal, to reduce the electric field near the gate oxide interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a high potential difference is applied between gate and drain terminal to enable power MOSFET operation, then the transistor can perform switching actions, but the electric field at the gate oxide interface becomes too large causing deterioration or destruction of the oxide layer
Solution Approach 1:
A shielding region with third conductivity type is introduced as an intermediary between the second doped region and the gate dielectric. This shielding region acts as a mediator that reduces the electric field strength at the gate oxide interface while allowing the high potential difference to remain between gate and drain terminals, thus protecting the oxide layer from deterioration while maintaining power MOSFET operation capability
Solution Approach 2:
The shielding region is locally positioned between the second doped region and the gate dielectric, creating a localized modification of the electric field distribution. This local quality change allows the electric field to be reduced specifically at the vulnerable gate oxide interface while maintaining the overall high voltage operation capability of the transistor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the shielding region effectively reduces the electric field at the gate oxide interface, preventing oxide deterioration and ensuring the transistor's operational integrity.
Implementation Method 1
a high potential difference is created between the gate and drain terminal. If the electric field at the gate interface is too large, a deterioration or destruction of the oxide layer can occur
Data Source
AI summary
The present disclosure relates to a semiconductor device and a method of manufacturing semiconductor device. The present disclosure relates particularly to MOSFET transistors. A semiconductor device according to the disclosure including: a first-conductivity-type substrate, a first-conductivity-type epitaxy layer including a JFET region and a second-conductivity-type shield region, two well regions including two source regions, gate oxide including a gate, a drain adjacent to the first-conductivity-type substrate, the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, the two well regions are adjacent to the first-conductivity-type epitaxy layer, the JFET region is located between the two well regions, the source contact region is the outermost layer and is adjacent to the two source regions, and the gate oxide is adjacent to the two well regions, the two source regions, and the JFET region.