SiC MOSFET Shielding Regions for Gate Dielectric Protection
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Solution Overview
Problem
SiC MOSFETs face challenges due to low electron mobility at the SiC-SiO2 interface and high breakdown fields, which affect the performance and reliability of power semiconductor devices, particularly in trench MOSFET technologies where the gate dielectric is prone to high electric fields.
Innovation Solution
A semiconductor device design featuring gate trenches in a SiC substrate with rows of source and body regions, and shielding regions to maximize the active channel area while protecting the gate dielectric from high electric fields, including the use of first and second shielding regions to provide three-dimensional shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep p-type implants are used to form JFET-like structure below the gate trench, then the gate dielectric is protected from high electric fields, but the on-resistance increases and the active channel area is reduced
Solution Approach 1:
The patent transitions from two-dimensional planar shielding structures to three-dimensional shielding structures that extend vertically below the gate trench. The shielding regions are formed at multiple depths and angles, creating a volumetric protection zone that shields the gate dielectric from high electric fields during avalanche breakdown while minimizing the lateral extent that would reduce active channel area.
Solution Approach 2:
The shielding regions are strategically positioned to provide localized protection only where high electric fields occur during avalanche breakdown, rather than uniformly across the entire device. The shielding structures are concentrated at specific locations below the gate trench where the electric field stress is highest, allowing maximum channel area to remain active while providing targeted protection.
2Loss of energy
If the active channel area is maximized to reduce on-resistance, then the shielding of the gate dielectric from high electric fields is insufficient
Solution Approach 1:
The patent employs three-dimensional shielding structures that extend vertically and at angles below the gate trench, utilizing the depth dimension to provide protection without consuming lateral space that would reduce the active channel area. This volumetric approach allows maximum channel width while maintaining adequate shielding.
Solution Approach 2:
The shielding regions are formed in advance during the device fabrication process, positioned below the gate trench before final device operation. This preliminary positioning ensures that the shielding structures are already in place to protect against avalanche breakdown electric fields before they occur, without requiring additional lateral space that would reduce channel area.
3Ease of manufacture
If conventional trench orientations are used, then manufacturing is simpler, but the surface roughness and steps due to 4° off-axis tilt cause unequal performance and reliability on the two trench side walls
Solution Approach 1:
The patent introduces asymmetric trench orientations that are specifically angled to compensate for the 4° off-axis crystal tilt. By orienting the trenches at specific angles relative to the crystal directions, one side wall of each trench aligns with a low-index crystal plane while the other side wall is intentionally made asymmetric, creating unequal but complementary surface conditions that balance the overall device performance.
Solution Approach 2:
The patent changes the trench orientation parameter from conventional vertical or symmetric angles to specific asymmetric angles that compensate for the crystal off-cut. By adjusting the trench angle parameter to match the crystal orientation, the surface roughness and step effects are equalized between the two side walls, achieving uniform electrical performance despite the inherent crystal asymmetry.
Data Source
AI summary
A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.