SiC MOSFET Intermediate Region Doping for Short-Circuit Reliability
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Solution Overview
Problem
Power SiC MOSFETs with solely an intermediate region doped with n-type dopants exhibit reduced short-circuit capability and increased Gate-Drain capacitance, leading to higher electric fields that can damage the gate oxide.
Innovation Solution
Incorporating an intermediate region with both n-type and p-type doped regions, where the doped regions have higher doping concentrations than the drift layer, reduces on-resistance and effectively lowers the electric field above the intermediate region, enhancing short-circuit capability and protecting the gate oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an intermediate region is doped with solely n-type dopants, then the device structure is simpler, but the short-circuit capability is reduced and Gate-Drain capacitance increases
Solution Approach 1:
The patent applies local quality by creating different doped regions (first doped region with n-type dopants and second doped region with p-type dopants) within the intermediate region. Each sub-region has specific doping characteristics tailored to fulfill different functions: the first doped region reduces on-resistance while the second doped region reduces Gate-Drain capacitance and improves short-circuit capability, thereby resolving the contradiction between structural simplicity and device reliability.
Solution Approach 2:
The intermediate region is constructed as a composite structure containing both n-type doped regions and p-type doped regions. This composite doping structure combines the benefits of both doping types to achieve superior electrical characteristics compared to单一 doping, specifically improving short-circuit capability while reducing Gate-Drain capacitance, thus resolving the technical contradiction.
2Ease of manufacture
If an intermediate region is doped with solely n-type dopants, then the manufacturing process is simpler, but the Gate-Drain capacitance increases leading to higher electric fields
Solution Approach 1:
The patent introduces a second doped region with p-type dopants in addition to the first doped region with n-type dopants. The p-type doping locally reduces the Gate-Drain capacitance, which in turn reduces the electric field strength in critical areas, protecting the gate oxide from damage while maintaining manufacturing feasibility through extended doping processes.
Solution Approach 2:
The patent converts the potentially harmful high electric field effect into a benefit by using p-type doped regions to reduce Gate-Drain capacitance. This reduces the electric field intensity that would otherwise damage the gate oxide, transforming a harmful factor into a protective mechanism while maintaining device performance.
3Reliability
If the doping concentration in the intermediate region is increased, then the on-resistance is reduced, but the electric field intensity increases
Solution Approach 1:
The patent divides the intermediate region into spatially separated first doped regions (n-type) and second doped regions (p-type). The n-type regions provide low on-resistance by increasing carrier concentration, while the p-type regions reduce Gate-Drain capacitance and thereby reduce electric field intensity. This local differentiation allows simultaneous optimization of both parameters without compromise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces on-resistance, maintains short-circuit behavior, and effectively decreases Gate-Drain capacitance, thereby improving the durability and performance of power semiconductor devices.
Implementation Method 1
The well regions comprise second dopants. The intermediate region is produced by introducing at least one of the first dopants or the second dopants into the drift layer
Data Source
AI summary
A power semiconductor device (1) is provided, comprisinga drift layer (2) of a first conductivity type,at least two well regions (3) of a second conductivity type being different from the first conductivity type, andat least one intermediate region (4), whereinthe at least two well regions (3) and the at least one intermediate region (4) are provided within the drift layer (2) at a first side,the at least one intermediate region (4) is provided between the at least two well regions (3), andthe at least one intermediate region (4) comprises at least one first doped region (5) of the first conductivity type and at least one second doped region (6) of the second conductivity type.


