SiC Power MOSFET JFET Structure for Short-Circuit Reliability
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Solution Overview
Problem
Current power MOSFETs face challenges in achieving high current densities and blocking high voltages while maintaining reliability and short circuit capability, with existing designs often compromising on performance parameters like channel mobility, threshold voltage, and on-state resistance.
Innovation Solution
The design incorporates a silicon carbide drift region with strategically doped wells and a JFET region, featuring a deeper, highly doped p-well structure that increases the depletion region width, reduces saturation drain current, and enhances pinch-off effects, thereby improving short circuit capability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional power MOSFET designs are used to achieve high current densities and block high voltages, then voltage blocking capability is improved, but short circuit capability and reliability deteriorate due to excessive power dissipation and internal temperature rise
Solution Approach 1:
The patent applies local quality by creating a JFET region with higher doping concentration specifically in the lower portion of the drift region, while keeping the upper drift region lightly doped for voltage blocking. This localized doping enhancement reduces saturation drain current and power dissipation during short circuit conditions without compromising the voltage blocking capability of the overall device structure.
Solution Approach 2:
The patent changes the doping concentration parameter locally by forming a JFET region with doping concentration higher than the surrounding drift region. This parameter change creates a narrower depletion region width in the JFET region, which reduces the saturation drain current and consequently lowers power dissipation and internal temperature rise during short circuit operation, improving reliability.
2Reliability
If deeper, highly doped p-well structures are implemented to reduce saturation drain current, then short circuit capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the drift region into functionally distinct zones: an upper lightly-doped drift region for voltage blocking and a lower JFET region with higher doping concentration for current saturation control. This segmentation allows each region to optimize its function independently, achieving improved short circuit capability through the doped JFET region while maintaining voltage blocking through the upper drift region, without requiring overly complex multi-layer doping structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the short circuit capability and reliability of power MOSFETs by reducing power dissipation and internal temperature rise under short circuit conditions, while maintaining high voltage blocking and switching performance.
Implementation Method 1
a deeper, highly doped p-well structure that increases the depletion region width, reduces saturation drain current, and enhances pinch-off effects
Implementation Method 2
a deeper, highly doped p-well structure that increases the depletion region width, reduces saturation drain current, and enhances pinch-off effects
Implementation Method 3
the gate electrode forms a capacitor with the channel region. Thus, only minimal charging and discharging current is required during switching
Implementation Method 4
a first well located in an upper portion of the silicon carbide drift region, the first well doped with dopants having a second conductivity type
Data Source
AI summary
A power semiconductor device has a semiconductor layer structure that includes a silicon carbide drift region having a first conductivity type, first and second wells in the silicon carbide drift region that are doped with dopants having a second conductivity type, and a JFET region between the first and second wells. The first and second wells each include a main well and a side well that is between the main well and the JFET region, and each side well includes a respective channel region. A doping concentration of the JFET region exceeds a doping concentration of the silicon carbide drift region, and a minimum width of an upper portion of the JFET region is greater than a minimum width of a lower portion of the JFET region.