SiC MOSFET Si Layer Thickness Optimization
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Solution Overview
Problem
SiC-based MOSFETs face high on-resistance due to high channel resistance, which is attributed to the high channel resistance and the Si/SiC interface affecting electron flow.
Innovation Solution
A semiconductor device structure with a Si layer of varying thickness between SiC regions, where the Si layer is thicker on the p channel region and thinner on the drift region, optimizing the Si layer thickness to reduce channel resistance and on-resistance, and using a gate insulating film to improve mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a SiC-based MOSFET is used to achieve high temperature operation and low loss, then the breakdown field strength and heat conductivity are improved, but the on-resistance increases due to high channel resistance
Solution Approach 1:
The patent applies local quality by creating different Si layer thicknesses in different regions: a first Si layer with thickness of 5-50nm on the channel region to reduce channel resistance, and a second Si layer with thickness of 2-20nm on the drift region. This localized variation in Si layer thickness optimizes electron mobility where needed while maintaining the high breakdown field strength properties of SiC in the drift region.
Solution Approach 2:
The patent uses a composite structure combining SiC and Si layers with specific thicknesses. The SiC substrate provides high breakdown field strength and heat conductivity, while the Si layers (with optimized thicknesses of 5-50nm on channel and 2-20nm on drift region) reduce channel resistance and improve electron mobility, creating a composite material system that achieves both high reliability and low on-resistance.
2Ease of manufacture
If a uniform Si layer thickness is used on all regions, then the manufacturing process is simplified, but the channel resistance and on-resistance cannot be optimized
Solution Approach 1:
The patent implements local quality by specifying different Si layer thicknesses for different regions: 5-50nm on the channel region and 2-20nm on the drift region. This localized differentiation optimizes channel resistance and electron mobility in the channel region while maintaining appropriate properties in the drift region, achieving performance optimization despite increased manufacturing complexity.
Solution Approach 2:
The patent applies parameter changes by establishing specific thickness ranges for Si layers in different regions (5-50nm on channel, 2-20nm on drift). These controlled parameter variations enable optimization of channel resistance and on-resistance, transforming the uniform structure into a differentiated structure that achieves superior electrical performance.
Data Source
AI summary
The semiconductor device of this embodiment includes: a first region of a first conductivity type SiC; a second region of a first conductivity type SiC, impurity concentration of first conductivity type of the second region being lower than impurity concentration of first conductivity type of the first region; a third region of a second conductivity type SiC provided between the first region and the second region; a Si layer provided on surfaces of the first, second, and third regions, a thickness of the Si layer on the third region being thicker than a thickness of the Si layer on the second region; a gate insulating film provided on the Si layer; and a date electrode provided on the gate insulating film.