SiC Power MOSFET Source Alignment to Prevent Parasitic NPN
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Solution Overview
Problem
Existing silicon carbide (SiC) power MOSFETs face reliability issues due to lithographic misalignment between p-well and N+ source regions, leading to asymmetric MOS channel lengths, increased ON resistance, and potential parasitic NPN transistor activation during extreme conditions.
Innovation Solution
A self-aligned manufacturing process is employed, involving multiple hard mask layers and selective etching to form self-aligned N+ source regions, combined with source trenches and highly doped P+ plug regions, to ensure precise alignment and removal of parasitic N+ source regions, thereby improving channel length uniformity and preventing parasitic transistor activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two separate masking steps are used to form p-well and N+ source regions, then the manufacturing process is simpler, but lithographic misalignment occurs resulting in asymmetric MOS channel lengths and increased ON resistance
Solution Approach 1:
The patent combines the formation of p-well and N+ source region masking into a single dual-purpose masking step. The first hard mask layer is patterned to define both the p-well regions and the N+ source regions simultaneously, eliminating lithographic misalignment between separate masking steps and ensuring uniform MOS channel lengths.
Solution Approach 2:
The patent segments the masking process by using multiple hard mask layers with different functions. The first hard mask layer is used for dual-purpose patterning of p-well and N+ source regions, while the second hard mask layer is used for selective etching to form source trenches. This segmentation allows precise control of each region while maintaining overall process simplicity.
2Manufacturing precision
If self-aligned technique with sidewall spacer deposition is used, then MOS channel length uniformity is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent extracts and eliminates the sidewall spacer deposition and etching steps from the self-aligned technique. Instead of using sidewall spacers to define the N+ source region alignment, the patent directly patterns both p-well and N+ source regions in a single masking step, achieving self-alignment without the complex spacer formation process.
Solution Approach 2:
The patent performs preliminary action by pre-defining the precise positions of both p-well and N+ source regions in the first hard mask layer before any implantation or etching steps. This preliminary patterning ensures that subsequent steps automatically achieve the desired alignment without requiring additional self-alignment mechanisms.
3Reliability
If N+ source regions are formed without selective masking, then the process is simpler, but parasitic NPN transistors are activated during extreme conditions
Solution Approach 1:
The patent applies local quality by using the second hard mask layer to selectively mask specific regions during the formation of source trenches. This selective masking allows the N+ source regions to be formed with different characteristics in different locations, preventing parasitic NPN transistor activation in critical areas while maintaining the desired structure in active regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process enhances MOS channel density, reduces ON resistance, increases dV/dt rating, suppresses false turn-on, and improves device reliability by eliminating parasitic NPN transistors and reducing gate capacitance.
Implementation Method 1
performing a p-type implant to form a first p-well region; implanting N type ions to form a N+ source region
Implementation Method 2
depositing a first hard mask layer on the SiC substrate; depositing a second hard mask layer on top of the first hard mask layer
Implementation Method 3
performing an etch back of at least a portion of the second hard mask layer to form a sidewall spacer; etching into the SiC substrate to form recessed source trench region
Data Source
AI summary
An embodiment relates to a method obtaining a silicon carbide wafer comprising a first conductivity type substrate and a first conductivity type drift layer, forming a second conductivity type first well region within the first conductivity type drift layer, forming a first conductivity type source region within the second conductivity type first well region, forming a second conductivity type plug region under the first conductivity type source region, forming a gate oxide layer, forming a patterned gate metal layer, depositing an interlevel dielectric (ILD) layer, forming a first patterned mask layer on top of the ILD layer, and etching the ILD layer and the first conductivity type source region using the first patterned mask layer, and forming a silicide layer, wherein the silicide layer is in contact with a vertical sidewall of the first conductivity type source region and at-least one second conductivity type region.