SiC MOSFET Source Ballasting for Short Circuit Resilience
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Solution Overview
Problem
Silicon carbide power devices exhibit inferior short circuit characteristics compared to similar silicon devices due to their low specific on-resistance and high thermal conductivity, which limits their performance in high voltage and high frequency applications.
Innovation Solution
The implementation of a silicon carbide planar MOSFET integrated device with source ballasting, where the channel region pitch is decoupled from the contact region pitch, allowing for increased channel density without corresponding contact density, thereby modifying source and channel resistances independently to improve short circuit characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If silicon carbide is used to fabricate power devices with low specific on-resistance and high thermal conductivity, then operating temperature and power level are improved, but short circuit characteristics deteriorate
Solution Approach 1:
The device is segmented into multiple parallel channels, each with its own source contact. This segmentation allows the total source resistance to be distributed across multiple paths, preventing excessive current concentration in any single channel during short circuit conditions, thereby improving overall short circuit characteristics while maintaining low on-resistance for normal operation
Solution Approach 2:
Different regions of the device are given different properties: the channel region is optimized for low resistance conduction during normal operation, while the source contact region is designed with specific geometric characteristics (such as reduced contact area or increased contact resistance) to provide current limiting during short circuit conditions, creating local quality differences that resolve the contradiction
Data Source
AI summary
A method for making an integrated device that includes a plurality of planar MOSFETs, includes forming a plurality of doped body regions in an upper portion of a silicon carbide substrate composition and a plurality of doped source regions. A first contact region is formed in a first source region and a second contact region is formed in a second source region. The first and second contact regions are separated by a JFET region that is longer in one planar dimension than the other. The first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region.