SiC MOSFET Source-Island Layout for Short-Circuit Withstand
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Solution Overview
Problem
Power semiconductor devices, particularly those based on silicon carbide (SiC) MOSFETs, face a trade-off between conduction losses and short-circuit withstand time, falling short of industry standards.
Innovation Solution
Incorporating an island region of a second conductivity type within the source region, which separates the island region from the well layer in a significant portion of its surface area, enhances short-circuit withstanding time without significantly increasing on-state resistance, achieved through additional p+ implantation and specific doping concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the source region doping concentration is increased to reduce conduction losses, then the on-state resistance decreases, but the short-circuit withstand time is reduced
Solution Approach 1:
The patent introduces an island region with different doping concentration (1E16 to 1E18 atoms/cm³) within the source region (1E19 to 1E21 atoms/cm³), creating local quality variation. This allows the source region to have high doping for low conduction losses in most areas, while the island region provides lower doping to extend short-circuit withstand time without significantly increasing overall on-state resistance
Solution Approach 2:
The patent changes the doping concentration parameter spatially by introducing the island region with doping concentration of 1E16 to 1E18 atoms/cm³ within the higher-doped source region. This parameter change allows optimization of both conduction losses and short-circuit withstand time by having different doping levels in different spatial locations
2Productivity
If the source region area is reduced to improve device integration, then the device density increases, but the short-circuit withstand time decreases
Solution Approach 1:
By introducing the island region with specific doping concentration (1E16 to 1E18 atoms/cm³) within the source region, the patent creates local quality that extends short-circuit withstand time. This allows the overall source region area to be reduced for better integration while the island region compensates for the reduced short-circuit performance
3Duration of action of stationary object
If additional structures are added to improve short-circuit withstand time, then the short-circuit performance improves, but the device complexity increases
Solution Approach 1:
The island region is nested within the source region, creating a hierarchical structure where a lower-doped region (1E16 to 1E18 atoms/cm³) is embedded within a higher-doped region (1E19 to 1E21 atoms/cm³). This nesting approach improves short-circuit withstand time without adding external structures, thereby minimizing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves short-circuit withstanding time by up to 15% while maintaining minimal impact on conduction losses, thereby optimizing the trade-off between these two critical performance metrics.
Implementation Method 1
Exemplarily, the island region reduces a cross section of the source region. Thus, the form of the source region and the island region might result in a slightly increased source resistance value. The island region modifies the source resistance in such a way so to enhance the short-circuit withstanding time
Data Source
AI summary
A power semiconductor device (10) comprises a semiconductor body (11) which includes a first main surface (12) and a second main surface (13), a gate insulator (14) arranged at the first main surface (12), and a gate electrode (15) separated from the semiconductor body (11) by the gate insulator (14). The semiconductor body (11) comprises a drift layer (16) of a first conductivity type, a well layer (27) of a second conductivity type being different from the first conductivity type and forming a first junction (18) to the drift layer (16), a source region (20) of the first conductivity type forming a second junction (21) to the well layer (27), and an island region (30) of the second conductivity type attaching the source region (20) such that the source region (20) separates the island region (30) from the well layer (27) in at least 50% of an island surface area of the island region (30) in the semiconductor body (11).