SiC MOSFET Source Recess Design for Gate Dielectric Reliability
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Solution Overview
Problem
Conventional silicon carbide (SiC) double implantation MOSFETs face issues with surface roughening due to high-temperature thermal treatment, leading to decreased breakdown voltage and reliability of the gate dielectric, and require lengthy epitaxial growth processes for alternative solutions.
Innovation Solution
A semiconductor device design with a silicon carbide substrate and layers of specific conductivity types, where the peak ion implantation concentration is positioned within the substrate, and a source recess is formed to inhibit surface roughening, allowing for a high breakdown voltage and improved gate dielectric reliability without the need for high-temperature treatments or epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-dose ion implantation is performed up to the surface of SiC followed by high-temperature thermal treatment at about 1600°C, then the n-type source region is activated, but surface roughening occurs on the source region leading to decreased breakdown voltage and reliability of the gate dielectric
Solution Approach 1:
The patent applies preliminary action by forming a protective oxide film on the SiC surface before ion implantation. This oxide film prevents direct exposure of the SiC surface to high-temperature thermal treatment during subsequent processing steps, thereby preventing surface roughening while still allowing ion implantation to proceed effectively for source region activation
Solution Approach 2:
The patent introduces an oxide film as an intermediary layer between the SiC surface and the ion implantation process. This intermediary layer protects the SiC surface from damage during thermal treatment while permitting the ion implantation to activate the source region, thus resolving the contradiction between reliability improvement and surface quality maintenance
2Reliability
If high-temperature thermal treatment at about 1600°C is used to activate the ion-implanted source region, then activation is achieved, but considerable damage occurs to the ion-implanted region causing surface roughening
Solution Approach 1:
The patent applies beforehand cushioning by forming an oxide film on the SiC surface prior to ion implantation and thermal treatment. This oxide film acts as a cushioning layer that absorbs and protects the SiC surface from the harmful effects of high-temperature thermal treatment, preventing surface roughening while allowing the ion-implanted source region to be properly activated
3Manufacturing precision
If epitaxial growth is used to form the p-type base region, then surface roughening is avoided, but the manufacturing process time increases significantly
Solution Approach 1:
The patent applies parameter changes by modifying the ion implantation conditions, specifically controlling the implantation depth and dose distribution to position the peak concentration within the substrate rather than at the surface. This parameter optimization allows the use of ion implantation instead of lengthy epitaxial growth, achieving both good surface quality and reduced manufacturing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves high breakdown voltage and reliability with reduced on-resistance and manufacturing time, while maintaining low contact resistance and improved gate dielectric performance.
Implementation Method 1
a p-well and a source region are formed by ion implantation
Implementation Method 2
the ion implantation is carried out under a high-dose condition up to the surface of SiC in a box profile, and the thermal treatment at a high temperature of about 1600°C is used
Data Source
Figure 1~2
Figure 3~5
Figure 6~8
AI summary
A semiconductor device includes an SiC substrate (101) of a first conductivity type or a second-conductivity type, an SiC layer (102) of the first conductivity type formed on a first main surface of the SiC substrate (101), a first SiC region (103) of the second conductivity type formed on a surface of the SiC layer (102), a second SiC region (104) of the first conductivity type formed within a surface of the first SiC region (103), a gate dielectric (105) continuously formed on the SiC layer (102), the second SiC region (104), and the surface of the first SiC region (103) interposed between the SiC layer (102) and the second SiC region (104), a gate electrode (106) formed on the gate dielectric (105), a first electrode (108) embedded in a trench selectively formed in a part where the first SiC region (103) adjoins the second SiC region (104), and a second electrode (107) formed on a second main surface of the SiC substrate (101).