SiC MOSFET Source Contact Design for Low On-Resistance
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Solution Overview
Problem
High power silicon carbide (SiC) devices face challenges with forward voltage degradation due to Basal Plane Dislocations and increased on-resistance at high blocking voltages and temperatures, limiting their efficiency in high power and high temperature applications.
Innovation Solution
The design includes a semiconductor device with a drift layer, well region, and source region, featuring a lateral source region and source contact regions, with a body contact region between source contact regions, optimized for high current density and reverse blocking voltage, using wide bandgap material like silicon carbide to reduce source resistance and enhance switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If bipolar operation is used to reduce drift layer resistance via conductivity modulation, then forward voltage drop is reduced, but forward voltage degradation occurs over time due to Basal Plane Dislocations in silicon carbide
Solution Approach 1:
The patent extracts the problematic bipolar operation from the device design and replaces it with unipolar MOSFET operation. By removing the bipolar mechanism that causes forward voltage degradation from BPDs, the device maintains stable electrical characteristics over time while still achieving low on-resistance through optimized drift layer design and conductivity modulation in the source region.
Solution Approach 2:
The patent changes the operational parameters from bipolar to unipolar mode, and modifies the drift layer doping concentration and thickness parameters to achieve optimal balance between blocking voltage and on-resistance. The source region doping is optimized to provide conductivity modulation without requiring bipolar operation, thus avoiding BPD-related degradation.
2Reliability
If blocking voltage is increased to 15 kV or more, then voltage blocking capability is improved, but on-resistance increases substantially due to increased drift layer thickness
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile in the drift layer with higher doping concentration near the source region and lower concentration toward the drain. This gradient profile allows the drift layer to support high blocking voltages while maintaining lower resistance in the high-field region. The source region is also locally optimized with specific doping to reduce contact resistance and improve current collection.
Solution Approach 2:
The patent employs composite material structures by combining the drift layer with a specially doped source region and well region. This composite structure allows different regions to perform different functions: the drift layer provides voltage blocking, while the source region provides low-resistance contact and carrier injection, achieving both high voltage capability and low on-resistance.
3Reliability
If drift layer thickness is increased to support higher blocking voltages, then voltage blocking capability is improved, but power dissipation increases due to bulk mobility reduction at high temperatures
Solution Approach 1:
The patent optimizes the drift layer thickness and doping concentration parameters to achieve the minimum required thickness for the desired blocking voltage while maintaining doping levels that preserve carrier mobility at high temperatures. The source region doping is increased to compensate for mobility reduction in the drift layer, ensuring low on-resistance even at elevated temperatures.
Data Source
AI summary
A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.