SiC-MOSFET Edge Structure to Suppress Stacking Fault Degradation
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Solution Overview
Problem
The integration of a freewheeling diode into a SiC-MOSFET substrate to reduce leakage current and on-resistance is hindered by crystal defects in SiC wafers, particularly stacking faults originating from the dicing surface, leading to energization deterioration and increased heat loss.
Innovation Solution
A semiconductor device with a built-in n-type hole annihilation region is introduced between the p-type termination region and the dicing surface, preventing hole recombination and subsequent stacking faults, thus minimizing energization deterioration and allowing for miniaturization of power modules without external diodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a freewheeling diode is incorporated into the SiC-MOSFET substrate to downsize the power module, then the module size is reduced and external diodes are eliminated, but crystal defects in the SiC wafer cause stacking faults that lead to energization deterioration and increased on-resistance
Solution Approach 1:
An n-type hole annihilation region is introduced as an intermediary structure between the p-type termination region and the dicing surface. This region acts as a mediator that captures and annihilates holes before they can reach the dicing surface and cause stacking faults, thereby preventing energization deterioration while maintaining the integrated diode structure
Solution Approach 2:
The n-type hole annihilation region is positioned to preemptively intercept holes in their path toward the dicing surface. By creating this protective barrier in advance, the structure prevents the formation of stacking faults before they can occur, eliminating the need for external diodes while maintaining reliability
2Reliability
If the n-type hole annihilation region is positioned closer to the dicing surface to better prevent stacking faults, then protection against energization deterioration is improved, but the distance from the p-type termination region increases, affecting the electric field distribution
Solution Approach 1:
The invention optimizes the positional parameters of the n-type hole annihilation region by specifying that it be positioned at a distance of 0.003 to 0.007 times the thickness of the drift layer from the dicing surface. This parameter optimization ensures effective hole annihilation while maintaining appropriate electric field distribution for reliable device operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses energization deterioration and on-resistance increase, enabling the miniaturization of power modules and converters by eliminating the need for external diodes and reducing power losses.
Implementation Method 1
A semiconductor device with a built-in n-type hole annihilation region is introduced between the p-type termination region and the dicing surface, preventing hole recombination and subsequent stacking faults
Data Source
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AI summary
An object of the present invention is to suppress energization deterioration due to crystal defects in a semiconductor device including SiC-MOSFET. To solve this problem, a semiconductor device of the present invention includes: an n--type epitaxial layer formed on a main surface of an n+-type SiC substrate; a p-type termination region that is annularly formed in the n--type epitaxial layer outside an active region; and an n-type hole annihilation region annularly formed in the n--type epitaxial layer outside the p-type termination region, apart from the p-type termination region. Then, the n-type hole annihilation region has a first end surface facing the p-type termination region, as well as a second end surface on the opposite side of the first end surface. When a depth of the n-type hole annihilation region is dTM, a depth of the p-type termination region is dNR, a thickness of the n--type epitaxial layer is dEpi, a distance from the first end surface of the n-type hole annihilation region to the second end surface thereof is LNR, and a distance from the first end surface of the n-type hole annihilation region to the periphery of the semiconductor substrate is |XNR|, these variables have the following relationship: dNR≥dTM, (|XNR|+dNR)≥dEpi, 0<LNR<|XNR|