SiC MOSFET Embedded Region Layout for Stacking Fault Suppression
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Solution Overview
Problem
The existing SiC-MOSFETs face issues with decreased withstand voltage and increased ON voltage due to the extension of stacking faults caused by body diode current, which deteriorates the characteristics of the MOSFET and body diode, and the provision of additional p-type regions below the p-type base region does not adequately address these issues.
Innovation Solution
Incorporating a plurality of first embedded regions of a second conductivity type immediately below the end portions of the base region in the SiC-MOSFET, which reduces the lifetime of holes in the drift layer and suppresses the extension of stacking faults, thereby increasing body diode current without affecting the conduction route or increasing ON voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Schottky barrier diode is provided in the MOSFET to divert diode current, then stacking fault extension is suppressed, but the region of the MOSFET decreases and ON voltage increases
Solution Approach 1:
An n-type region is introduced as an intermediary structure between the p-type base region and the drift layer. This n-type region acts as a mediator that redirects hole current away from the drift layer while maintaining the MOSFET's active region. The n-type region with its specific impurity concentration creates a potential barrier that prevents holes from reaching the drift layer, thereby suppressing stacking fault extension without requiring a Schottky barrier diode that would reduce the active area.
2Reliability
If additional p-type regions are provided below the p-type base region to reduce hole lifetime, then stacking fault extension is suppressed, but withstand voltage decreases
Solution Approach 1:
Instead of uniformly adding p-type regions throughout the drift layer, the invention locally introduces an n-type region with specific impurity concentration (1×10^15 to 1×10^17 atoms/cm³) at a specific depth (0.5 to 2.0 μm from the drift layer surface). This localized modification creates a hole-trapping zone only where needed to suppress stacking faults, while the rest of the drift layer maintains its original properties and withstand voltage capability.
Solution Approach 2:
The invention changes the impurity concentration parameter of the drift layer locally by introducing an n-type region with controlled doping levels. By carefully selecting the impurity concentration (1×10^15 to 1×10^17 atoms/cm³) and depth position (0.5 to 2.0 μm), the hole lifetime is reduced in the n-type region without significantly affecting the overall drift layer parameters that determine withstand voltage.
3Quantity of substance
If the width of the n-type region adjacent to the end portion of the p-type base region is increased, then body diode current capacity increases, but electrical field concentration increases and withstand voltage decreases
Solution Approach 1:
The invention optimizes the width parameter of the n-type region to balance two competing requirements. By setting the width to 0.5 to 2.0 μm, the n-type region provides sufficient cross-sectional area to handle body diode current while maintaining a narrow enough profile to avoid excessive electrical field concentration at the edges, thereby preserving withstand voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the extension of stacking faults, increases body diode current, and maintains withstand voltage, ensuring stable current characteristics without altering the conduction route or increasing ON voltage.
Implementation Method 1
The plurality of first embedded regions are formed adjacent to a lower surface of the base region. A lifetime of a hole decreases in a region of the drift layer sandwiched between two first embedded regions adjacent to each other
Implementation Method 2
known is a technique of providing a Schottky barrier diode (SBD) in a MOSFET and flowing diode current into the SBD
Implementation Method 3
a reverse pn diode referred to as a body diode is formed by a pn junction made up of an n-type drift layer and a p-type base region
Data Source
AI summary
An object of the present disclosure is to suppress decrease in withstand voltage and increase in ON voltage and to increase body diode current. An SiC-MOSFET includes: a source region formed on a surface layer of a base region; a gate electrode facing a channel region which is a region of the base region sandwiched between a drift layer and the source region via a gate insulating film; a source electrode having electrically contact with the source region; and a plurality of first embedded regions of a second conductivity type formed adjacent to a lower surface of the base region. The plurality of first embedded regions are formed immediately below at least both end portions of the base region, and three or more first embedded regions are formed to be separated from each other.