SiC MOSFET Strain Engineering for Channel Mobility
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Solution Overview
Problem
Silicon carbide (SiC) MOSFETs have lower channel mobility than expected, limiting the performance and resistance reduction of power semiconductor devices, despite their superior physical properties.
Innovation Solution
The semiconductor device incorporates a 4H—SiC crystal with a lattice spacing difference in the well region and drain region, applying strain to the surface of the semiconductor layer to enhance channel mobility by altering the lattice spacing and energy split width at the conduction band bottom, thereby improving electron mobility and reducing ON resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate insulating film forming conditions are used, then the device structure is simple, but the channel mobility remains lower than expected from SiC material limits
Solution Approach 1:
The patent applies strain to the SiC crystal lattice by controlling the lattice spacing in the well region relative to the drift region. This parameter change in the crystal structure modifies the energy split width at the conduction band bottom, thereby increasing electron mobility in the channel without fundamentally changing the device architecture or requiring complex multi-step film formation processes
Solution Approach 2:
The invention introduces a well region with a specific lattice spacing that differs from the drift region, creating a localized strained area beneath the gate electrode. This local modification of crystal structure properties enhances channel mobility specifically in the region where electrons flow, while maintaining the overall simplicity of the MOSFET structure
2Manufacturing precision
If strain is applied to increase energy split width, then channel mobility increases, but the device structure becomes more complex
Solution Approach 1:
The strain is applied locally to the well region beneath the gate electrode, creating a focused area of modified crystal structure. This localized strain application enhances channel mobility where needed without requiring strain throughout the entire device structure, thereby minimizing added complexity
Solution Approach 2:
The patent modifies the energy split width at the conduction band bottom through strain-induced lattice spacing changes. This parameter change in the electronic band structure directly increases electron mobility in the channel, achieving performance improvement through fundamental material property modification rather than structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The strain application increases electron mobility and reduces ON resistance by collecting electrons in a valley with lower effective mass, enhancing the performance of SiC MOSFETs beyond conventional improvements.
Implementation Method 1
applying strain to the surface of the semiconductor layer to enhance channel mobility by altering the lattice spacing and energy split width at the conduction band bottom
Implementation Method 2
The third semiconductor region has a lattice spacing different from a lattice spacing of the silicon carbide crystal of 4H—SiC
Data Source
AI summary
According to one embodiment, a semiconductor device includes a gate electrode, a first semiconductor region, a second semiconductor region of a first conductivity type, a third semiconductor region of a second conductivity type and a fourth semiconductor region of the first conductivity type. The first semiconductor region includes a silicon carbide crystal of 4H—SiC. The second semiconductor region includes a first portion opposing the gate electrode and is provided between the gate electrode and the first semiconductor region. The third semiconductor region has a lattice spacing different from a lattice spacing of the silicon carbide crystal of 4H—SiC and is provided between the gate electrode and the second semiconductor region. The fourth semiconductor region is selectively provided on the third semiconductor region.