SiC Trench MOSFET Super Junction for Low On-Resistance Reliability
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Solution Overview
Problem
The increase in on-resistance of silicon carbide MOSFETs due to reflux current flowing through the built-in diode leads to a decrease in reliability, particularly when used as a switching element for inductive loads.
Innovation Solution
A vertical MOSFET with a trench-gate structure and super junction (SJ) structure is designed with a specific inclination of the silicon carbide layer faces and alternating p-type and n-type regions, combined with a gate electrode and insulating layer, to reduce on-resistance and enhance breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the built-in diode is used to conduct reflux current, then the MOSFET can handle inductive loads, but stacking faults grow in the silicon carbide layer due to carrier recombination energy, causing on-resistance to increase and reliability to decrease
Solution Approach 1:
The patent extracts the harmful function of the built-in diode by removing or isolating the pn junction region that causes stacking fault growth during reflux current conduction, while preserving the MOSFET's ability to handle inductive loads through alternative current path design
Solution Approach 2:
The patent introduces an external diode as an intermediary component to conduct the reflux current, separating the reflux current function from the MOSFET's main current path and preventing stacking fault growth in the silicon carbide layer while maintaining inductive load handling capability
2Reliability
If the n-type impurity concentration is increased to reduce on-resistance, then the MOSFET achieves lower on-resistance, but the breakdown voltage decreases
Solution Approach 1:
The patent applies different impurity concentrations to different regions of the silicon carbide layer, with higher n-type impurity concentration in regions requiring low resistance and appropriate doping levels in regions requiring high breakdown voltage, achieving both low on-resistance and high breakdown voltage through spatially varying material properties
Solution Approach 2:
The patent creates a composite doped structure with multiple regions having different impurity concentrations and doping types, combining the benefits of low resistance paths and high breakdown voltage regions within a single semiconductor device
3Reliability
If the trench-gate structure and SJ structure are combined to scale down the SJ structure, then the on-resistance is further reduced, but the device complexity increases
Solution Approach 1:
The patent segments the semiconductor device into distinct functional regions including trench-gate structures and super junction structures with alternating doped regions, allowing independent optimization of each segment while achieving overall low on-resistance through the combined architecture
Solution Approach 2:
The patent utilizes vertical dimensionality in the trench-gate structure extending into the silicon carbide layer, creating a three-dimensional architecture that achieves low on-resistance through increased effective channel area without proportionally increasing planar device footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces on-resistance and maintains reliability by managing electric field intensity and reflux current, enhancing the performance of silicon carbide MOSFETs in high-temperature and low-loss operations.
Implementation Method 1
The SJ structure relaxes electric field intensity in a semiconductor by a depletion layer extending in the lateral direction in the p-type region and the n-type region, and realizes the high breakdown voltage of the MOSFET
Implementation Method 2
a gate insulating layer provided between the gate electrode and the silicon carbide layer
Data Source
AI summary
A semiconductor device of an embodiment includes a SiC layer including a first face parallel to first direction and second direction perpendicular to the first direction, a trench extending in the first direction, a gate electrode, an n-type first SiC region, a p-type second SiC region between the first SiC region and the trench, extending in the second direction, an n-type third SiC region extending in the second direction, and alternately and repeatedly provided with the second SiC region in the first direction, a p-type fourth SiC region between the third SiC region and the first face, an n-type fifth SiC region between the fourth SiC region and the first face. The first face is inclined with respect to a (0001) face by 0.1 to 8 degrees in a <11-20> direction, and the first direction is along the <11-20> direction, and the second direction is along a <1-100> direction.


