SiC MOSFET Threshold Voltage Control via Base Layer Doping
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Solution Overview
Problem
Conventional silicon carbide (SiC) MOSFETs face issues with increased ON resistance and variability in threshold voltage due to current flowing directly beneath the gate electrode, leading to crystal defects and reliability concerns, as the threshold voltage is often lower than the forward voltage of the built-in PN diode.
Innovation Solution
The semiconductor device and manufacturing method involve increasing the impurity concentration of the p-type base layer, thickening the gate insulating film, and using a p-type poly-silicon gate electrode with higher impurity concentration to elevate the threshold voltage of the MOSFET beyond the forward voltage of the built-in PN diode, thereby preventing current flow through the PN junction and reducing crystal defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the threshold voltage of the MOSFET is lower than the forward voltage of the built-in PN diode, then the device can operate with lower gate voltage, but current flows directly beneath the gate electrode causing crystal defects and reliability issues
Solution Approach 1:
The patent changes the threshold voltage parameter of the MOSFET by adjusting the impurity concentration of the p-type base layer and the gate insulating film thickness, ensuring that the threshold voltage becomes higher than the forward voltage of the built-in PN diode. This parameter change prevents direct current flow beneath the gate electrode, eliminating crystal defects and improving device reliability.
2Reliability
If the impurity concentration of the p-type base layer is increased to raise the threshold voltage, then the threshold voltage exceeds the PN diode forward voltage, but the ON resistance may increase
Solution Approach 1:
The patent optimizes the impurity concentration of the p-type base layer to a specific range that balances threshold voltage elevation with ON resistance control. By carefully selecting this parameter, the threshold voltage is raised above the PN diode forward voltage while maintaining acceptable ON resistance levels.
Solution Approach 2:
The patent applies different impurity concentrations to different regions: the p-type base layer has a specific impurity concentration range to raise threshold voltage, while the source and drain regions have higher impurity concentrations to maintain low ON resistance. This local quality differentiation resolves the contradiction between threshold voltage stability and energy loss.
3Reliability
If the gate insulating film is thickened to increase the threshold voltage, then the threshold voltage becomes higher than the PN diode forward voltage, but the gate control efficiency may decrease
Solution Approach 1:
The patent sets the gate insulating film thickness within a specific range that provides sufficient threshold voltage elevation while maintaining adequate gate control efficiency. This optimized thickness parameter ensures the threshold voltage exceeds the PN diode forward voltage without excessive gate control loss.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, and a gate electrode. A threshold voltage of the semiconductor device is higher than forward voltage of a built-in PN diode constituted by the second semiconductor layer, the semiconductor substrate, and the first semiconductor layer. Thus, when high electric potential is applied to a source electrode and the built-in PN diode is driven, the generation of crystal effects may be suppressed.